XRT83SL314(2003) Просмотр технического описания (PDF) - Exar Corporation
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XRT83SL314 Datasheet PDF : 85 Pages
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PRELIMINARY
XRT83SL314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.5
TABLE 45: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION
GLOBAL REGISTER (0XE4H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
MclkT1out1 MCLKT1OUT Select
R/W
0
D6
MclkT1out0 MclkT1out[1:0] is used to program the MCLKT1out pin. By default,
0
the output clock is 1.544MHz.
00 = 1.544MHz
01 = 3.088MHz
10 = 6.176MHz
11 = 12.352MHz
D5
MclkE1out1 MCLKE1OUT Select
R/W
0
D4
MclkE1out0 MclkE1out[1:0] is used to program the MCLKE1out pin. By
0
default, the output clock is 2.048MHz.
00 = 2.048MHz
01 = 4.096MHz
10 = 8.192MHz
11 = 16.384MHz
D3
Reserved This Register Bit is Not Used
R/W
0
D2
Reserved This Register Bit is Not Used
R/W
0
D1
Reserved This Register Bit is Not Used
R/W
0
D0
Reserved This Register Bit is Not Used
R/W
0
TABLE 46: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION
GLOBAL REGISTER (0XE5H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
LCV/OFLW Line Code Violation / Counter Overflow Monitor Select
R/W
0
This bit is used to select the monitoring activity between the LCV
and the counter overflow status. When the 16-bit LCV counter sat-
urates, the counter overflow condition is activated. By default, the
LCV activity is monitored by bit D4 in register 0x05h.
0 = Monitoring LCV
1 = Monitoring the counter overflow status
D6
CNTRDEN Line Code Violation Counter Read Enable
R/W
0
This bit enables the 16-bit LCV counter contents to be read from
bits D[7:0] in register 0xE8h. If a counter reaches full scale, it sat-
urates and remains at FFFFh until a reset is initiated in register
0xE6h. By default, the LCV counter readback function is disabled.
0 = Disabled
1 = Enables the 16-bit LCV Counters for Readback
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