datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать

XRT7296 Просмотр технического описания (PDF) - Exar Corporation

Номер в каталоге
Компоненты Описание
производитель
XRT7296 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
XRT7296
ELECTRICAL CHARACTERISTICS (See Figure 8 )
Test Conditions: VDD = 5V ± 5%, TA = -40C to +85C, unless otherwise specified. All timing characteristics
are measured with 10pF loading.
Symbol Parameter
Min.
Typ.
Max.
Units
AC Electrical Characteristics
# +/; , - -/+ '  *(
&
&
&&
.
# +/; , - -/+ ' (
"
&
&
.

# +/;   '.  %.(


$
# +/; $++  '.  %.(


? 07  # $++   ? 


:= 07  # $++  :+ 
&
I
075  #   0   +- 
)



# +/; , - -/+
&
&
&&
.

# +/;   '.  %.(


$
# +/; $++  '.  %.(


? 07  # $++   ? 


:= 07  # $++  :+ 
&


#= +/;   '.  %.(


$
#= +/; $++  '.  %.(


I
0=7 579  #=   0  
+- 


DC Electrical Characteristics
<
<
 , +- <+ 
, +- , 
"&
&
&&
<


<
, 2 <+ 
<:
, :1 <+ 
<=
=, , 2 <+  =?K*
<=:
=, , :1 <+  =?K

, ; , 

<J "
57
< * &
&
<
<
<

<
<
<
± 

0 %) ' , K<(
*&
*&


,  /  /

  /  /

$

$
Notes:
1 When the encoder is enabled, a handling delay of four and a half TCLK clock cycles for B3ZS and five and half clock cycles for HDB3
always exists between TPDATA/TNDATA and TTIP/TRING. The handling delay is reduced to two clock cycles when the encoder
is disabled.
2 When the decoder is enabled, a handling delay of six and a half RCLK clock cycles will always exist between RPDATA/RNDATA
and RPOS/RNEG/RNRZ. The handling delay is reduced to one and half RCLK clock cycles when the decoder is disabled.
3 Supply current is measured with transmitter sending all ones AMI signal and with Transmit Level (TXLEV) set to high.
4 All inputs except pin 19, 20 and pin 26.
Specifications are subject to change without notice
 
&

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]