XC161
Derivatives
Preliminary
General Device Information
2.2
Pin Configuration and Definition
The pins of the XC161 are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E*) and C*) mark pins to be used as alternate external
interrupt inputs, C*) marks pins that can have CAN/SDLM interface lines assigned to
them.
NC 1
NC 2
P20.12/RSTOUT 3
NMI 4
VSSP 5
VDDP 6
P6.0/CS0/CC0 7
P6.1/CS1/CC1 8
P6.2/CS2/CC2 9
P6.3/CS3/CC3 10
P6.4/CS4/CC4 11
P6.5/HOLD/CC5 12
P6.6/HLDA/CC6 13
P6.7/BREQ/CC7 14
P7.4/CC28IO/C*) 15
P7.5/CC29IO/C*) 16
P7.6/CC30IO/C*) 17
P7.7/CC31IO/C*) 18
VSSP 19
VDDP 20
P9.0/SDA0/CC16io/C*) 21
P9.1/SCL0/CC17io/C*) 22
P9.2/SDA1/CC18io/C*) 23
P9.3/SCL1/CC19io/C*) 24
P9.4/SDA2/CC20IO 25
P9.5/SCL2/CC21IO 26
VSSP 27
VDDP 28
P5.0/AN0 29
P5.1/AN1 30
P5.2/AN2 31
P5.3/AN3 32
P5.4/AN4 33
P5.5/AN5 34
P5.10/AN10/T6EUD 35
P5.11/AN11/T5EUD 36
XC161
108 NC
107 NC
106 P0H.1/AD9
105 P0H.0/AD8
104 VSSP
103 VDDP
102 P0L.7/AD7
101 P0L.6/AD6
100 P0L.5/AD5
99 P0L.4/AD4
98 P0L.3/AD3
97 P0L.2/AD2
96 P0L.1/AD1
95 P0L.0/AD0
94 P20.5/EA
93 P20.4/ALE
92 P20.2/READY
91 P20.1/WR/WRL
90 P20.0/RD
89
VSSP
88
VDDP
87 P4.7/A23/C*)
86 P4.6/A22/C*)
85 P4.5/A21/C*)
84 P4.4/A20/C*)
83 P4.3/A19
82 P4.2/A18
81 P4.1/A17
80 P4.0/A16
79
VSSI
78
VDDI
77 P3.15/CLKOUT/FO
76 P3.13/SCLK0/E*)
75 P3.12/BHE/WRH/
74 TMS
/E*)
73 TDO
Figure 2 Pin Configuration (top view)
Data Sheet
5
V1.0, 2002-03