WM8771 Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8771 Datasheet PDF : 44 Pages
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WM8771
MASTER CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
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Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
MCLK System clock pulse width high
tMCLKH
MCLK System clock pulse width low
MCLK System clock cycle time
tMCLKL
tMCLKY
MCLK Duty cycle
TEST CONDITIONS
MIN
11
11
28
40:60
TYP
MAX
UNIT
ns
ns
ns
60:40
Table 1 Master Clock Timing Requirements
w
PP Rev 2.0 December 2001
8
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