WM8771 Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8771 Datasheet PDF : 44 Pages
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WM8771
DSP LATE MODE
In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8771 on the first BCLK
rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2, 3 and 4 data
follow DAC channel 1 left data (Figure 16).
1/fs
DACLRC
BCK
DIN1
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
12
MSB
n-1 n 1 2
LSB
n-1 n 1 2
Input Word Length (IWL)
CHANNEL 4
RIGHT
NO VALID DATA
n-1 n
1
Figure 16 DSP Late Mode Timing Diagram – DAC data input
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of
BCLK as the low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The
right channel ADC data is contiguous with the left channel data (Figure 17).
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
12
n-1 n 1 2
n-1 n
1
MSB
LSB
Input Word Length (IWL)
Figure 17 DSP Late Mode Timing Diagram – ADC data output
In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and
the data words for the other 6 channels. No BCLK edges are allowed between the data words. The
word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right, DAC4 left, DAC4
right.
w
PP Rev 2.0 December 2001
21
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