V54C365404VD Просмотр технического описания (PDF) - Mosel Vitelic Corporation

Номер в каталоге

Компоненты Описание

производитель

V54C365404VD

HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

V54C365404VD(L)

6.2 Write Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3, 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND NOP

WRITE A

READ B

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, I/O’s

CAS latency = 3

tCK3, I/O’s

CAS latency = 4

tCK4, I/O’s

DIN A0

don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

DIN A0

don’t care don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

DIN A0

don’t care don’t care don’t care

DOUT B0 DOUT B1 DOUT B2

Input data for the Write is ignored.

Input data must be removed from the I/O’s at least one clock

cycle before the Read dataAPpears on the outputs to avoid

data contention.

7. Burst Write with Auto-Precharge

Burst Length = 2, CAS latency = 2, 3, 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND

BANK A

ACTIVE

NOP

CAS latency = 2

I/O’s

CAS latency = 3

I/O’s

CAS latency = 4

I/O’s

NOP

WRITE A

Auto-Precharge

DIN A0

DIN A0

DIN A0

NOP

NOP

NOP

NOP

tWR

tRP

* DIN A1

tWR

tRP

* DIN A1

tWR

tRP

DIN A1

*

* Begin Autoprecharge

Bank can be reactivated after trp

NOP

V54C365404VD(L) Rev. 0.9 September 2001

21

Share Link: