µPD75P3036
* 3.4 Recommended Connection of Unused Pins
Pin
Recommended connection
P00/INT4
Connect to VSS or VDD
P01/SCK
Connect to VSS or VDD via a resistor individually
P02/SO/SB0
P03/SI/SB1
Connect to VSS
P10/INT0 to P12/INT2 Connect to VSS or VDD
P13/TI0
P20/PTO0
Input status : connect to VSS or VDD via a resistor individually.
P21/PTO1
Output status: open
P22/PTO2/PCL
P23/BUZ
P30/LCDCL
P31/SYNC
P32, P33
P40 to P43
Connect to VSS
P50 to P53
P60/KR0 to P63/KR3 Input status : connect to VSS or VDD via a resistor individually.
P70/KR4 to P73/KR7 Output status: open
P80/TI1
P81/TI2
P82/AN6
P83/AN7
S12 to S23
Open
S24/BP0 to S31/BP7
COM0 to COM3
VLC0 to VLC2
Connect to VSS
BIAS
Connect to VSS only when VLC0 to VLC2 are all not used.
In other cases, leave open.
XT1Note
Connect to VSS or VDD
XT2Note
Open
AN0 to AN5
Connect to VSS or VDD
VPP
Connect to VDD directly
Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use
the internal feedback resistor).
14