LTC1400CS8TR Просмотр технического описания (PDF) - Linear Technology

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LTC1400CS8TR

Complete SO-8, 12-Bit, 400ksps ADC with Shutdown

Linear Technology 

TYPICAL APPLICATIO S

TMS320C50 Code for Circuit

LTC1400

THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO TMS320C50

FRAME SYNC PULSE IS GENERATED FROM TFSX

*Initialization*

.mmregs

;- - Initialized data memory to zero

.ds

0F00h

DATA0 .word 0

DATA1 .word 0

DATA2 .word 0

DATA3 .word 0

DATA4 .word 0

DATA5 .word 0

;- - Set up the ISR vector

.ps

080Ah

rint : B

RECEIVE

xint : B

TRANSMIT

trnt : B

TREC

txnt : B

TTRANX

;- - Setup the reset vector

.ps 0A00h

.entry

START:

; Defines global symbolic names

; Initialize data to zero

; Begin sample data location

;.

; Location of data

;.

;.

; End sample data location

; Serial ports interrupts

; 0A;

; 0C;

; 0E;

; 10;

*TMS32C050 Initialization*

SETC INTM

; Temporarily disable all interrupts

LDP #0

; Set data page pointer to zero

OPL #0834h, PMST ; Set up the PMST status and control register

LACC #0

SAMM CWSR

; Set software wait state to 0

SAMM PDWSR

;

*Configure Serial Port*

SPLK #0038h, TSPC ; Set TDM Serial Port

; TDM = 0 Stand Alone mode

; DLB = 0 Not loop back

; FO = 0 16 Bits

; FSM = 1 Burst Mode

; MCM = 1 CLKX is generated internally

; TXM = 1 FSX as output pin

; Put serial port into reset

; (XRST = RRST =0)

SPLK #00F8h, TSPC ; Take Serial Port out of reset

; (XRST = RRST = 1)

SPLK #0FFFFh, IFR ; Clear all the pending interrupts

*Start Serial Communication*

SACL TDXR

; Generate frame sync pulse

SPLK #040h, IMR ; Turn on TRNT receiver interrupt

CLRC INTM

; Enable interrupt

CLRC SXM

; For Unipolar input, set for right shift

; with no sign extension

MAR *AR7

; Load the auxiliary register pointer with seven

LAR AR7, #0F00h ; Load the auxiliary register seven with #0F00h

; as the begin address for data storage

WAIT: NOP

; Wait for a receive interrupt

NOP

;

NOP

;

SACL TDXR

; !! regenerate the frame sync pulse

B WAIT

;

; - - - - - - - end of main program - - - - - - - - - - ;

*Receiver Interrupt Service Routine*

TREC:

LAMM TRCV

; Load the data received from LTC1400

SFR

; Shift right two times

SFR

;

AND #1FFFh, 0

; ANDed with #1FFFh

; For converting the data to right

; justified format

;

SACL *+, 0

; Write to data memory pointed by AR7 and

; increase the memory address by one

LACC AR7

;

SUB #0F05h,0

; Compare to end sample address #0F05h

BCND END_TRCV, GEQ ; If the end sample address has exceeded jump

to END_TRCV

;

SPLK #040h, IMR ; Else Re-enable the TRNT receive interrupt

RETE

; Return to main program and enable interrupt

*After Obtained the Data from LTC1400, Program Jump to END_TRCV*

END_TRCV:

SPLK #002h, IMR ; Enable INT2 for program to halt

CLRC INTM

SUCCESS:

B SUCCESS

*Fill the Unused Interrupt with RETE, to avoid program get “lost”*

TTRANX:

RETE

RECEIVE:

RETE

TRANSMIT:

RETE

INT2:

B halt

; Halts the running CPU

1400fa

15

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