TS80C52X2-VICR Просмотр технического описания (PDF) - Temic Semiconductors
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TS80C52X2-VICR Datasheet PDF : 54 Pages
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TS80C52X2
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA.
10.4.15 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
INTERNAL
CLOCK
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
STATE4 STATE5
P1 P2 P1 P2
XTAL2
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
P0
DATA
SAMPLED
FLOAT
P2 (EXT)
READ CYCLE
RD
P0
P2
WRITE CYCLE
WR
P0
P2
PCL OUT
DATA
SAMPLED
FLOAT
INDICATES ADDRESS TRANSITIONS
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
DPL OR Rt OUT
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DPL OR Rt OUT
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PORT OPERATION
MOV DEST P0
OLD DATA NEW DATA
P0 PINS SAMPLED
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
P1, P2, P3 PINS SAMPLED
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
RXD SAMPLED
Figure 25. Clock Waveforms
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
Rev. B - Jan. 25, 1999
53
Preliminary
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