AD7721AR Просмотр технического описания (PDF) - Analog Devices
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AD7721AR Datasheet PDF : 16 Pages
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AD7721
TIMING CHARACTERISTICS1, 2 (AVDD= +5 V ؎ 5%; DVDD= +5 V ؎ 5%; AGND = DGND = 0 V, REFIN = +2.5 V
unless otherwise noted)
Parameter
Limit at TMIN, TMAX
(A, S Versions)
Units
Conditions/Comments
Serial Interface
fCLK3
tCLK LO
tCLK HI
t1
t24
t3
t4
t5
t6
t7
t85
t9
100
15
0.45 × tCLK
0.45 × tCLK
tCLK
tCLK HI – 10
20
tCLK HI
tCLK LO
25
0
0
20
32 × tCLK
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns max
ns nom
ns nom
ns max
ns min
ns min
ns max
ns nom
Master Clock Frequency
15 MHz for Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
DRDY High Time
RFS Low to SCLK Falling Edge Setup Time
RFS Low to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Delay
RFS to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of RFS
Period between Consecutive DRDY Rising Edges
Parallel Interface
fCLK3
tCLK LO
tCLK HI
Read Operation
t10
t11
t12
Write Operation
t13
t14
t15
100
10
0.45 × tCLK
0.45 × tCLK
2 × tCLK
30
32 × tCLK
35
20
0
kHz min
MHz max
ns min
ns min
ns nom
ns max
ns nom
ns min
ns min
ns min
Master Clock Frequency
10 MHz for Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
DRDY High Time
Data Access Time after Falling Edge of DRDY
Period between Consecutive DRDY Rising Edges
WR Pulse Width
Data Valid to WR High Setup Time
Data Valid to WR High Hold Time
NOTES
The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum.
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2All digital outputs are timed with the load circuit below and, except for t2, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last.
3The AD7721 is production tested with fCLK at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character-
ization to operate with CLK frequencies down to 100 kHz.
4t2 is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V.
5t8 and t15 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus
relinquish time of the part and, as such, is independent of external bus loading capacitance.
1.6mA IOL
TO
OUTPUT
PIN
CL
50pF
+1.6V
200A IOH
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4–
REV. A
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