AD7721AR Просмотр технического описания (PDF) - Analog Devices
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AD7721AR Datasheet PDF : 16 Pages
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AD7721–SPECIFICATIONS1 (AVDD = +5 V ؎ 5%; DVDD = +5 V ؎ 5%; AGND = DGND = 0 V,
fCLK = 15 MHz, REFIN = +2.5 V; TA = TMIN to TMAX, unless otherwise noted)
Parameter
A Version
S Version
Units
Test Conditions/Comments
SERIAL MODE ONLY
STATIC PERFORMANCE
Resolution
Minimum Resolution for Which
No Missing Codes Is Guaranteed
Differential Nonlinearity
Integral Nonlinearity
DC CMRR
Offset Error2
Unipolar Mode
Bipolar Mode
Full-Scale Error 2, 3
Unipolar Mode
Bipolar Mode
Unipolar Offset Drift
Bipolar Offset Drift
ANALOG INPUTS
Signal Input Span (VIN1–VIN2)
Bipolar Mode
Unipolar Mode
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
Differential Input Impedance
REFERENCE INPUTS
VREFIN
REFIN Input Current
DYNAMIC SPECIFICATIONS
Signal to (Noise + Distortion)
Total Harmonic Distortion
Frequency Response
0 kHz–210 kHz
229.2 kHz
259.01 kHz to 14.74 MHz
CLOCK
CLK Duty Ratio
VCLKH, CLK High Voltage
VCLKL, CLK Low Voltage
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
IDD (Total from AVDD, DVDD)
Power Consumption
Power Consumption
16
12
±8
± 16
70
± 3.66
± 3.66
± 4.88
± 4.88
0.05
0.04
± VREFIN/2
0 to VREFIN
AVDD
0
1.6
2 fCLK
20.8
2.4 to 2.6
200
74
–78
± 0.05
–3
–72
45 to 55
0.7 × DVDD
0.3 × DVDD
2.0
0.8
10
10
4.0
0.4
4.75/5.25
4.75/5.25
28.5
150
100
16
12
±8
± 16
70
± 3.66
± 3.66
± 4.88
± 4.88
0.05
0.04
Bits
Bits min
LSB typ
LSB max
dB min
mV max
mV max
mV max
mV max
mV/°C typ
mV/°C typ
Guaranteed 12 Bits Monotonic
16-Bit Operation
Bipolar Mode
Typically 0.61 mV
Typically 0.61 mV
Typically 0.61 mV
Typically 1.22 mV
± VREFIN/2
0 to VREFIN
AVDD
0
1.6
2 fCLK
20.8
2.4 to 2.6
200
74
–78
± 0.05
–3
–72
45 to 55
0.7 × DVDD
0.3 × DVDD
2.0
0.8
10
10
4.0
0.4
4.75/5.25
4.75/5.25
28.5
150
100
Volts max
Volts max
Volts
Volts
pF typ
MHz
kΩ typ
UNI = VIH
UNI = VIL
Guaranteed by Design
With 15 MHz on CLK Pin
V min/V max
µA typ
dB min
dB max
dB max
dB min
dB min
Input Bandwidth 0 kHz to 210 kHz
Input Bandwidth 0 kHz to 229.2 kHz
% max
V min
V max
For Specified Operation
CLK Uses CMOS Logic
V min
V max
µA max
pF max
V min
V max
|IOUT| ≤ 200 µA
|IOUT| ≤ 1.6 mA
V min/V max
V min/V max
mA max
mW max
µW max
Digital Inputs Equal to 0 V or DVDD
Active Mode
Standby Mode
NOTES
1Operating temperature range is as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.
2Applies after calibration at temperature of interest.
3Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin.
Specifications subject to change without notice.
–2–
REV. A
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