TDA9109S Просмотр технического описания (PDF) - STMicroelectronics
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TDA9109S Datasheet PDF : 30 Pages
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TDA9109/S
HORIZONTAL SECTION
Operating Conditions
Symbol
VCO
Parameter
R0(Min.) Minimum Oscillator Resistor
C0(Min.) Minimum Oscillator Capacitor
F(Max.) Maximum Oscillator Frequency
OUTPUT SECTION
I12m
HOI
Maximum Input Peak Current
Horizontal Drive Output Maximum Current
Test Conditions
Pin 6
Pin 5
Pin 12
Pin 26, Sunk current
Min. Typ. Max. Unit
6
kΩ
390
pF
150 kHz
5 mA
30 mA
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
SUPPLY AND REFERENCE VOLTAGES
VCC
VDD
ICC
IDD
VREF-H
VREF-V
IREF-H
IREF-V
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Horizontal Reference Voltage
Vertical Reference Voltage
Max. Sourced Current on VREF-H
Max. Sourced Current on VREF-V
1st PLL SECTION
Pin 29
Pin 32
Pin 29
Pin 32
Pin 13, I = -2mA
Pin 21, I = -2mA
Pin 13
Pin 21
10.8 12 13.2 V
4.5 5 5.5 V
50
mA
5
mA
7.4 8 8.6 V
7.4 8 8.6 V
5 mA
5 mA
HpolT
VVCO
Delay Time for detecting polarity change
(see Note 3)
VCO Control Voltage (Pin 7)
Vcog VCO Gain (Pin 7)
Hph Horizontal Phase Adjustment (see Note 4)
Vbmin
Vbtyp
Vbmax
Horizontal Phase Setting Value (Pin 8) (see Note 4)
Minimum Value
Typical Value
Maximum Value
IPll1U PLL1 Filter Current Charge
IPll1L
f0 Free Running Frequency
Sub-Address 02 - Byte xxx10000
df0/dT Free Running Frequency Thermal Drift
(No drift on external components) (see Note 5)
Free Running Frequency Adjustment
f0(Min.) Minimum Value
f0(Max.) Maximum Value
CR PLL1 Capture Range
FF Forced Frequency FF1 Byte 11xxxxxx
FF2 Byte 10xxxxxx
Pin 1
0.75
ms
VREF-H = 8V
f0
fH(Max.)
R0 = 6.49kΩ, C0 = 820pF,
dF/dV = 1/11R0C0
% of Horizontal Period
Sub-Address 01
Byte x1111111
Byte x1000000
Byte x0000000
PLL1 is Unlocked
PLL1 is Locked
R0 = 6.49kΩ, C0 = 820pF,
f0 = 0.97/8R0C0
1.3
6.2
17.1
±10
2.8
3.4
4.0
±140
±1
22.8
-150
V
V
kHz/V
%
V
V
V
µA
mA
kHz
ppm/C
Sub-Address 02
Byte xxx11111
Byte xxx00000
0.8
f0
1.3
f0
R0 = 6.49kΩ, C0 = 820pF,
from f0+0.5kHz to 4.5f0
f0 adjsusted to 22.8kHz
fH(Min.)
fH(Max.)
100
23.5 kHz
kHz
Sub-Address 02
2f0
3f0
Notes : 3. This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.
4. See Figure 10 for explanation of reference phase.
5. These parameters are not tested on each unit. They are measured during our internal qualification.
7/30
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