TDA9109 Просмотр технического описания (PDF) - STMicroelectronics

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TDA9109

LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

STMicroelectronics 

TDA9109/SN

HORIZONTAL SECTION

Operating Conditions

Symbol

Parameter

VCO

R0(Min.)

C0(Min.)

F(Max.)

Minimum Oscillator Resistor

Minimum Oscillator Capacitor

Maximum Oscillator Frequency

OUTPUT SECTION

I12m

HOI

Maximum Input Peak Current

Horizontal Drive Output Maximum Current

Test Conditions

Pin 6

Pin 5

Pin 12

Pin 26, Sunk current

Min. Typ. Max. Unit

6

kΩ

390

pF

150 kHz

5 mA

30 mA

Electrical Characteristics (VCC = 12V, Tamb = 25oC)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

SUPPLY AND REFERENCE VOLTAGES

VCC Supply Voltage

VDD Supply Voltage

ICC Supply Current

IDD Supply Current

VREF-H Horizontal Reference Voltage

VREF-V Vertical Reference Voltage

IREF-H Max. Sourced Current on VREF-H

IREF-V Max. Sourced Current on VREF-V

1st PLL SECTION

Pin 29

Pin 32

Pin 29

Pin 32

Pin 13, I = -2mA

Pin 21, I = -2mA

Pin 13

Pin 21

10.8 12 13.2 V

4.5 5 5.5 V

50

mA

5

mA

7.4 8 8.6 V

7.4 8 8.6 V

5 mA

5 mA

HpolT Delay Time for detecting polarity change

(see Note 3)

Pin 1

0.75

ms

VVCO VCO Control Voltage (Pin 7)

Vcog VCO Gain (Pin 7)

Hph Horizontal Phase Adjustment (see Note 4)

VREF-H = 8V

f0

fH(Max.)

R0 = 6.49kΩ, C0 = 820pF,

dF/dV = 1/11R0C0

% of Horizontal Period

1.3

6.2

17.1

±10

V

V

kHz/V

%

Vbmin

Vbtyp

Vbmax

Horizontal Phase Setting Value (Pin 8) (see Note 4)

Minimum Value

Typical Value

Maximum Value

Sub-Address 01

Byte x1111111

Byte x1000000

Byte x0000000

2.8

V

3.4

V

4.0

V

IPll1U PLL1 Filter Current Charge

IPll1L

PLL1 is Unlocked

PLL1 is Locked

±140

µA

±1

mA

f0 Free Running Frequency

R0 = 6.49kΩ, C0 = 820pF,

22.8

kHz

f0 = 0.97/8R0C0

df0/dT Free Running Frequency Thermal Drift

(No drift on external components) (see Note 5)

-150

ppm/C

CR PLL1 Capture Range

R0 = 6.49kΩ, C0 = 820pF,

from f0+0.5kHz to 4.5f0

fH(Min.)

fH(Max.)

90

25 kHz

kHz

FF Forced Frequency FF1 Byte 11xxxxxx

Sub-Address 02

2f0

FF2 Byte 10xxxxxx

3f0

Notes : 3. This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.

4. See Figure 10 for explanation of reference phase.

5. These parameters are not tested on each unit. They are measured during our internal qualification.

6. This PLL capture range may be obtained only if f0 is captured (for instance bu adjusting R0). If not, more margin must be provided

between fH (Min.) and f0, to cope with the components spread.

7/30

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