TDA7500A Просмотр технического описания (PDF) - STMicroelectronics
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TDA7500A Datasheet PDF : 41 Pages
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EXTERNAL MEMORY INTERFACE (EMI) SRAM MODE
Characteristics
Address Valid and CS Assertion Pulse Width
Address Valid to RD or WR Assertion
RD or WR Assertion Pulse Width
RD or WR Negation to RD or WR Assertion
RD or WR Negation to Address not Valid
Address Valid to Input Data Valid
RD Assertion to Input Data Valid
RD Negation to Data Not Valid (Data Hold Time)
Address Valid to WR Negation
Data Setup Time to WR Negation
Data Hold Time from WR Negation
WR Assertion to Data Valid
WR Negation to Data High-Z (Note 1)
WR Assertion to Data Active
Figure 12. External Memory Interface SRAM Read Cycle.
SRA_D
[7:0]
SRA_D
[13:8]
add. [7:0]
add. [13:8]
ALE
DRD
TDA7500A
40MHz
Unit
Min.
Max.
89
--
ns
23
--
ns
45
--
ns
39
--
ns
5
--
ns
--
72
ns
--
35
ns
0
--
ns
73
--
ns
32
--
ns
5
--
ns
--
18
ns
--
23
ns
5
--
ns
data
Figure 13. External Memory Interface SRAM Write Cycle.
SRA
[7:0]
add. [7:0]
data
SRA
[13:8]
add. [13:8]
ALE
DWR
25/40
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