TDA7500A Просмотр технического описания (PDF) - STMicroelectronics
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TDA7500A Datasheet PDF : 41 Pages
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SAI INTERFACE
Figure 1. SAI Timings
SDI0-3
Valid
TDA7500A
LRCKR
SCKR
(RCKP=0)
t sckpl
Valid
t lrh
tlrs
tsdih
tsckph
tdt
tsdis
t sckr
Timing
Description
tsckr
Minimum Clock Cycle
tdt
SCKR active edge to data out valid
tlrs
LRCK setup time
tlrh
LRCK hold time
tsdid
SDI setup time
tsdih
SDI hold time
tsckph Minimum SCK high time
tsckpl
Minimum SCK low time
Note TDSP = dsp master clock cycle time = 1/FDSP
Figure 2. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
Value
4TDSP
10
5
5
15
15
0.35 tsckr
0.35 tsckr
LRCKR (#68)
SCKR (#67)
LEFT
RIGHT
SDI0,1,2 (#62, #63, #64)
LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
19/40
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