TB62726AFNA Просмотр технического описания (PDF) - Toshiba

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TB62726AFNA

TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC

Toshiba 

TOSHIBA

Timing diagram

CLOCK

n=01 2 3 4 5 6 7 8 9 101112131415

SERIAL-IN

LATCH

ENABLE

OUT0

OUT1

OUT3

TB62726AFNA

5V

0V

5V

0V

5V

0V

5V

0V

On

Off

On

Off

On

Off

OUT15

On

Off

5V

SERIAL-OUT

0V

Warning :

Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit.

Note 2 :

The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a High-level, latch

circuit doesn’t hold data, and it passes from theInput to the output. When ENABLE terminal is Low-level, output

terminal OUT0~OUT15 respond to the data, and on & off does.

And, when ENABLE terminal is a High-level, it offs with the output terminal regardless of the data.

TB62726AFNA (Ver.09) 2002, Nov. 6th page 3/11

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