STK14C88-CF45 Просмотр технического описания (PDF) - Cypress Semiconductor
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STK14C88-CF45 Datasheet PDF : 20 Pages
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STK14C88
Hardware Mode Selection
E
W
HSB
A13 - A0 (hex)
H
X
H
X
L
H
H
X
L
L
H
X
X
X
L
X
Mode
Not Selected
Read SRAM
Write SRAM
Nonvolatile STORE
I/O
Output High Z
Output Data
Input Data
Output High Z
Power
Standby
Active
Active
lCC2
Notes
–
19
–
12
Hardware STORE Cycle
ns Symbols
No.
ig Standard Alternate
Parameter
s 22
tSTORE
e 23
tDELAY
D 24
tRECOVER
25
tHLHX
ew 26
tHLBL
tHLHZ
tHLQZ
tHHQX
STORE Cycle Duration
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
Hardware STORE Low to STORE Busy
ded for N HSB (IN)
Figure 8. Hardware STORE Cycle
25
tHLHX
22
tSTORE
24
tRECOVER
men HSB (OUT)
Not Recom DQ (DATA OUT)
HIGH IMPEDANCE
27
tHLBL
23
tDELAY
DATA VALID
STK14C88
Min Max
– 10
1
–
– 700
15 –
– 300
Units Notes
ms 13
s 13
ns 13, 14
ns
–
ns
–
HIGH IMPEDANCE
DATA VALID
Notes
12. HSB STORE operation occurs only if an SRAM write is done since the last nonvolatile cycle. After the STORE (if any) completes, the part goes into standby mode,
inhibiting all operations until HSB rises
13. E and G low, W high for output behavior.
14. tRECOVER is only applicable after tSTORE is complete.
Document Number: 001-52038 Rev. *C
Page 8 of 20
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