ST72F60K2U1 Просмотр технического описания (PDF) - STMicroelectronics
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ST72F60K2U1
STMicroelectronics
ST72F60K2U1 Datasheet PDF : 117 Pages
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ST7260
6 RESET AND CLOCK MANAGEMENT
6.1 RESET
The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: a low voltage
(LVD) reset, a watchdog reset and an external re-
set at the RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 4096 CPU clock cy-
cle delay from the time that the oscillator becomes
active.
6.1.1 Low Voltage Detector (LVD)
Low voltage reset circuitry generates a reset when
VDD is:
■ below VIT+ when VDD is rising,
■ below VIT- when VDD is falling.
During low voltage reset, the RESET pin is held low,
thus permitting the MCU to reset other devices.
It is recommended to make sure that the VDD sup-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
6.1.3 External Reset
The external reset is an active low input signal ap-
plied to the RESET pin of the MCU.
As shown in Figure 12, the RESET signal must
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger at the RESET pin is pro-
vided to improve noise immunity.
Figure 9. Low Voltage Detector functional Diagram
VDD
LOW VOLTAGE
DETECTOR
FROM
WATCHDOG
RESET
RESET
INTERNAL
RESET
Figure 10. Low Voltage Reset Signal Output
VIT+
VDD
VIT-
6.1.2 Watchdog Reset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devic-
es in the same way as the low voltage reset (Fig-
ure 9).
RESET
Note: Hysteresis (VIT+-VIT-) = Vhys
Figure 11. Temporization timing diagram after an internal Reset
VIT+
VDD
Addresses
Temporization (4096 CPU clock cycles)
$FFFE
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