SST34HF1621C Просмотр технического описания (PDF) - Silicon Storage Technology

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SST34HF1621C

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

Silicon Storage Technology 

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

Data Sheet

Product Identification

The Product Identification mode identifies the device as the

SST34HF16x1C and manufacturer as SST. This mode

may be accessed by software operations only. The hard-

ware device ID Read operation, which is typically used by

programmers cannot be used on this device because of

the shared lines between flash and SRAM in the multi-chip

package. Therefore, application of high voltage to pin A9

may damage this device. Users may use the software

Product Identification operation to identify the part (i.e.,

using the device ID) when using multiple manufacturers in

the same socket. For details, see Tables 4 and 5 for soft-

ware operation, Figure 17 for the Software ID Entry and

Read timing diagram and Figure 26 for the ID Entry com-

mand sequence flowchart.

TABLE 2: Product Identification

Manufacturer’s ID

ADDRESS

BK0000H

Device ID

SST34HF16x1C

BK0001H

DATA

00BFH

734BH

T2.1 1252

Note: BK = Bank Address (A19-A18)

Product Identification Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Note that the Software ID Exit/CFI Exit

command is ignored during an internal Program or Erase

operation. See Table 5 for software command codes, Fig-

ure 19 for timing waveform and Figure 26 for a flowchart.

SRAM Operation

With BES1# low, BES2 and BEF# high, the

SST34HF16x1C operate as either 128K x16, 256K x16, or

512K x16 CMOS SRAM, with fully static operation requir-

ing no external clocks or timing strobes. The

SST34HF16x1C SRAM is mapped into the first 512

KWord address space. When BES1#, BEF# are high and

BES2 is low, all memory banks are deselected and the

device enters standby. Read and Write cycle times are

equal. The control signals UBS# and LBS# provide access

to the upper data byte and lower data byte. For SRAM

Read and Write data byte control modes of operation, see

Table 4.

SRAM Read

The SRAM Read operation of the SST34HF16x1C is con-

trolled by OE# and BES1#, both have to be low with WE#

and BES2 high for the system to obtain data from the out-

puts. BES1# and BES2 are used for SRAM bank selection.

OE# is the output control and is used to gate data from the

output pins. The data bus is in high impedance state when

OE# is high. Refer to the Read cycle timing diagram, Fig-

ure 6, for further details.

SRAM Write

The SRAM Write operation of the SST34HF16x1C is con-

trolled by WE# and BES1#, both have to be low, BES2

must be high for the system to write to the SRAM. During

the Word-Write operation, the addresses and data are ref-

erenced to the rising edge of either BES1#, WE#, or the

falling edge of BES2 whichever occurs first. The write time

is measured from the last falling edge of BES#1 or WE# or

the rising edge of BES2 to the first rising edge of BES1#, or

WE# or the falling edge of BES2. Refer to the Write cycle

timing diagrams, Figures 7 and 8, for further details.

©2006 Silicon Storage Technology, Inc.

6

S71252-03-000

8/06

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