SP8505 Просмотр технического описания (PDF) - Signal Processing Technologies
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SP8505 Datasheet PDF : 12 Pages
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R/C
tW
BUSY
Converter
Mode
Data
BUS
tB
tDBC
Acquire
Data Valid
tAP
t DBE
Convert
tC
tHDR and tHL
Hi-Z State
Acquire
tA
t DB
Data Valid
Convert
Hi-Z State
Figure 5. Convert Mode Timing — R/C Pulse LOW, Outputs Enabled After Conversion
Series may draw excessive current. In normal
operation, this is not a problem because both pins
will be soldered together. However, during evalu-
ation, incoming inspection, repair, etc., where the
potential of a “Hot Socket” exists, care should be
taken to apply power to the SP85XX Series only
after it has been socketed.
Minimizing “Glitches”
Coupling of external transients into an analog-to-
digital converter can cause errors which are difficult to
debug. In addition to the discussions earlier on layout
considerations for supplies, bypassing and grounding,
there are several other useful steps that can be taken to
get the best analog performance out of a system using
the SP85XX Series. These potential system problem
sources are particularly important to consider when
developing a new system, and looking for the causes
of errors in breadboards.
First, care should be taken to avoid glitches during
critical times in the sampling and conversion process.
Since the SP85XX Series has an internal sample/hold
function, the signal that puts it into the hold state (R/C
going LOW) is critical, as it would be on any sample/
hold amplifier. The R/C falling edge should have a 5
to 10ns transition time, low jitter, and have minimal
ringing, especially during the 20ns after it falls.
R/C
tW
BUSY
tB
tDBC
Converter
Mode
Data
BUS
Acquire
tDD
Hi-Z State
Data
Valid
tAP
t DBE
Convert
tC
tHDR and tHL
Hi-Z State
Acquire
tA
tAP
Convert
Data
Valid
Hi-Z State
Figure 6. Read Mode Timing — R/C Pulse HIGH, Outputs Enabled Only When R/C is High
51
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