UPD98401AGD-MML Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD98401AGD-MML

ATM SAR CHIP

NEC => Renesas Technology 

µPD98401A

1.3 Bus Monitor Pins

The bus monitor pins indicate the type of data under DMA transfer. These five pins are enabled when the BME bit

of the GMR register is set to 1; they go into a high-impedance state when the BME bit is 0.

Pin Name

DBMD

DBML

DBMF

DBMR

DBVC

Pin No.

192

193

194

206

206

I/O

O

3-state

O

3-state

O

3-state

O

3-state

O

3-state

I/O Level

CMOS

CMOS

CMOS

CMOS

CMOS

Function

DMA Bus Monitor Data.

This pin indicates that the payload of an AAL-5 cell is under DMA

transfer. This pin is enabled when the BME bit of the GMR register is

set to 1, and goes into a high-impedance state when the BME bit is 0.

The DBMD signal changes in synchronization with the falling of the

ATTN_B signal. The high level of this signal indicates that the

payload of an ALL-5 packet transmit/receive cell is under DMA

transfer, and low level indicates that the other data is being

transferred.

DMA Bus Monitor Last.

If one-word data currently under DMA transfer satisfies any of the

following conditions, this pin goes high in synchronization with output

of the data.

• Last 1 word of last cell of AAL-5 packet

• 1-word data to be written to last word of receive buffer

• Last 1-word data of last cell of receive packet in which MAX.

NUMBER OF SEGMENTS error has occurred

When this pin is low, it indicates that the data is other than above.

This pin is enabled when the BME bit of the GMR register is set to 1; it

goes into a high-impedance state when the bit is 0.

DMA Bus Monitor First.

This pin indicates that the data under DMA transfer is the start cell of

a receive AAL-5 packet. This pin is enabled when the BME bit of the

GMR register is set to 1; it goes into a high-impedance state when the

bit is 0. This pin goes high in synchronization with the last word data

of the first cell of an AAL-5 packet.

DMA Bus Monitor Remaining.

This pin indicates that the number of cells remaining in the transmit

buffer is equal to, or has dropped below the value assigned to the RCS

register. This pin is enabled when the BME bit of the GMR register is set

to 1; it goes into a high-impedance state when the bit is 0.

DMA Bus Monitor VC.

This pin indicates that the data currently being transferred by DMA is

that of the VC for which the VCP bit in the receive VC table is set to 1.

This pin is asserted active in synchronization with the falling of

ATTN_B. It is enabled when the BME bit of the GMR register is set to

1, and goes into a high-impedance state when the bit is 0.

12

Data Sheet S12100EJ3V0DS00

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