CXD1812 Просмотр технического описания (PDF) - Sony Semiconductor
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CXD1812 Datasheet PDF : 56 Pages
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CXD1812Q/R
2. Sub CPU Write Registers
Normally set at low for reserved registers and bits.
2-1. CONFIG0 (configuration 0) register (address 00HEX)
bit 7:
CINTPOL (sub CPU interrupt polarity)
High: The XINT pin becomes high-active. When the register is inactive, the low state is
established.
Low: The XINT pin becomes low-active. When the register is inactive, high impedance is
established.
bit 6:
M/S SEL (master/slave select)
This bit is valid only when M/S EN (bit 5) is high.
High: Set this bit high when a slave drive is used.
Low: Set this bit low when a master drive is used.
bit 5:
M/S EN (master/slave mode enable)
Set this bit as follows according to the number of drives connected to ATAPI I/F.
High: Set this bit high when two drives are connected to ATAPI I/F. One is used as the master
drive and the other is the slave drive.
Low: Set this bit low when only one drive is connected to ATAPI I/F.
bit 4:
RESERVED
bit 3:
EXCKSL (EXCK select)
The frequency of EXCK clock signal for picking up subcodes from CD DSP is determined by this
bit. The sub CPU sets this register according to the clock frequency and the playback speed of the
XTL1 pin. (Max. frequency of EXCK clock signal is 1MHz.)
High: The EXCK frequency is 1/48 the frequency of XTL1. When the frequency of the XTL1 pin is
more than 32MHz, this bit is set high.
Low: The EXCK frequency is determined to be 1/32 the frequency of XTL1. When the frequency
of the XTL1 pin is not more than 32MHz, this bit is set low.
bit 2:
DISMCLK (disable MCLK output)
High: The MCLK pin is fixed at low.
Low: The clock signal of the same frequency as that of the XTL1 pin is output from the MCLK pin.
bit 1:
DISHCLK (disable HCLK output)
High: HCLK pin is fixed at low.
Low: The frequency divider clock signal of half the frequency of XTL1 pin is output from HCLK pin.
bit 0:
RAMSIZE (RAM size)
High: When a 4M-bit DRAM is connected, set this bit high.
Low: When a DRAM of up to 2M bits is connected, set this bit low.
2-2. CONFIG1 (configuration 1) register (address 01HEX)
bit 7:
SWOPEN (sync window open)
High: A window for Sync mark detection is opened. In this case, the internal Sync protection circuit
is disabled.
Low: A window for Sync mark detection is controlled by the internal Sync protection circuit.
bit 6 to 4: SYCNGC2 to 0 (sync NG count 2 to 0)
Set "010" for these bits.
bit 3:
RESERVED
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