SI4702-C19 Просмотр технического описания (PDF) - Silicon Laboratories

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SI4702-C19

BROADCAST FM RADIO TUNER FOR PORTABLE APPLICATIONS

Silicon Laboratories 

Si4702/03-C19

Table 7. 2-Wire Control Interface Characteristics1,2,3

(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

SCLK Frequency

fSCL

0

—

400

kHz

SCLK Low Time

tLOW

1.3

—

—

µs

SCLK High Time

tHIGH

0.6

—

—

µs

SCLK Input to SDIO Setup

(START)

tSU:STA

0.6

—

—

µs

SCLK Input to SDIO Hold (START)

SDIO Input to SCLK Setup

SDIO Input to SCLK Hold4,5

SCLK input to SDIO Setup (STOP)

tHD:STA

tSU:DAT

tHD:DAT

tSU:STO

0.6

—

—

µs

100

—

—

ns

0

—

900

ns

0.6

—

—

µs

STOP to START Time

tBUF

1.3

—

—

µs

SDIO Output Fall Time

tf:OUT

20 + 0.1 Cb

—

250

ns

SDIO Input, SCLK Rise/Fall Time

tf:IN

tr:IN

20 + 0.1 Cb

—

300

ns

SCLK, SDIO Capacitive Loading

Cb

—

—

50

pF

Input Filter Pulse Suppression

tSP

—

—

50

ns

Notes:

1. When VIO = 0 V, SCLK and SDIO are low impedance.

2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high

until after the 1st start condition.

3. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

4. As a 2-wire transmitter, the Si4702/03-C19 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to

comply with the 0 ns tHD:DAT specification.

5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be

violated so long as all other timing parameters are met.

10

Rev. 1.1

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