HD6417032F20 Просмотр технического описания (PDF) - Renesas Electronics

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HD6417032F20

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7030 Series

Renesas Electronics 

8.9 Wait State Control............................................................................................................. 166

8.10 Bus Arbitration.................................................................................................................. 169

8.10.1 Operation of Bus Arbitration ............................................................................... 170

8.10.2 BACK Operation ................................................................................................. 171

8.11 Usage Notes ...................................................................................................................... 172

8.11.1 Usage Notes on Manual Reset ............................................................................. 172

8.11.2 Usage Notes on Parity Data Pins DPH and DPL ................................................. 175

8.11.3 Maximum Number of States from BREQ Input to Bus Release.......................... 175

Section 9 Direct Memory Access Controller (DMAC) ............................................ 179

9.1 Overview........................................................................................................................... 179

9.1.1 Features ................................................................................................................ 179

9.1.2 Block Diagram ..................................................................................................... 181

9.1.3 Pin Configuration................................................................................................. 182

9.1.4 Register Configuration......................................................................................... 183

9.2 Register Descriptions ........................................................................................................ 184

9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 184

9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 184

9.2.3 DMA Transfer Count Registers 0–3 (TCR0–TCR3) ........................................... 185

9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 185

9.2.5 DMA Operation Register (DMAOR)................................................................... 190

9.3 Operation........................................................................................................................... 192

9.3.1 DMA Transfer Flow............................................................................................. 192

9.3.2 DMA Transfer Requests ...................................................................................... 194

9.3.3 Channel Priority ................................................................................................... 196

9.3.4 DMA Transfer Types ........................................................................................... 201

9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 208

9.3.6 DMA Transfer Ending Conditions....................................................................... 216

9.4 Examples of Use ............................................................................................................... 217

9.4.1 DMA Transfer between On-Chip RAM and Memory-Mapped External

Device .................................................................................................................. 217

9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory .......... 218

9.4.3 Example of DMA Transfer Between On-Chip A/D Converter and External

Memory................................................................................................................ 219

9.5 Usage Notes ...................................................................................................................... 220

Section 10 16-Bit Integrated Timer Pulse Unit (ITU) .............................................. 223

10.1 Overview........................................................................................................................... 223

10.1.1 Features ................................................................................................................ 223

10.1.2 Block Diagram ..................................................................................................... 226

Rev. 7.00 Jan 31, 2006 page xvii of xxvi

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