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SABC504 Просмотр технического описания (PDF) - Infineon Technologies

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производитель
SABC504
Infineon
Infineon Technologies 
SABC504 Datasheet PDF : 71 Pages
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C504
CPU
The C504 is efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient
use of program memory results from an instruction set consisting of 44% one-byte, 41%
two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions
are executed in 1.0 µs (24 MHz: 500 ns, 40 MHz: 300 ns).
Special Function Register PSW (Address D0H)
Reset Value: 00H
Bit No. MSB
LSB
D7H D6H D5H D4H D3H D2H D1H D0H
D0H
CY
AC
F0 RS1 RS0 OV
F1
P PSW
Bit
Function
CY
Carry Flag
Used by arithmetic instructions.
AC
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0
General Purpose Flag 0
RS1
Register Bank Select Control bits
RS0
These bits are used to select one of the four register banks.
RS1 RS0 Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
OV
Overflow Flag
Used by arithmetic instruction.
F1
General Purpose Flag 1
P
Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/
even number of “one” bits in the accumulator.
Data Sheet
11
2000-05

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