MYSON
TECHNOLOGY
MTP805
(Rev. 0.9)
USBADR (r/w) :USB device address and enable.
ENUSB = 1 → Enable USB function, clear while chip reset.
USBadr :
USB device address, clear while chip reset or USB bus reset.
INTFLG0 (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051’s INT0 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
RC0I = 1 → No action.
= 0 → Clear RC0I flag.
TX0I = 1 → No action.
= 0 → Clear TX0I flag.
TX1I = 1 → No action.
= 0 → Clear TX1I flag.
TX2I = 1 → No action.
= 0 → Clear TX2I flag.
RstI = 1 → No action.
= 0 → Clear RstI flag.
SusI = 1 → No action.
= 0 → Clear SusI flag.
INTFLG0 (r) :
RC0I
TX0I
TX1I
TX2I
RstI
SusI
Interrupt flag.
= 1 → Endpoint 0 has completed a receive transfer and save the data in RC0FIFO.
= 1 → Endpoint 0 has completed a transmit transfer and empty TX0FIFO.
= 1 → Endpoint 1 has completed a transmit transfer and empty TX1FIFO.
= 1 → Endpoint 2 has completed a transmit transfer and empty TX2FIFO.
= 1 → Indicates the USB bus reset condition.
= 1 → Indicates the USB bus suspend request (no bus activity for 3ms).
INTEN0 (w) : Interrupt enable.
RC0IE = 1 → Enable RC0I interrupt.
TX0IE = 1 → Enable TX0I interrupt.
TX1IE = 1 → Enable TX1I interrupt.
TX2IE = 1 → Enable TX2I interrupt.
RstIE = 1 → Enable RstI interrupt.
SusIE = 1 → Enable SusI interrupt.
INTFLG1 (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051’s INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
RsmI = 1 → No action.
= 0 → Clear RsmI flag.
KbdI = 1 → No action.
= 0 → Clear KbdI flag.
MsI = 1 → No action.
= 0 → Clear MsI flag.
INTFLG1 (r) :
RsmI
KbdI
MsI
Interrupt flag.
= 1 → Indicates the USB bus RESUME condition in suspend mode.
= 1 → Indicates a low input has been detected on anyone of the KSI pins.
= 1 → Indicates a low input has been detected on the MSCLK pin.
INTEN1 (w) : Interrupt enable.
PS2KB = 1 → Enable the pull up resistors on DP/PS2CLK and DM/PS2DATA pins.
FclkE = 1 → Enable the CPU’s faster clock, MUST be cleared before power-down.
Revision 0.9
- 10 -
2000/07/19