RC4200AN Просмотр технического описания (PDF) - Fairchild Semiconductor

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производитель

RC4200AN

Analog Multiplier

Fairchild Semiconductor 

RC4200

Divider Circuit with Offset Adjustment

+VREF

PRODUCT SPECIFICATION

R1

VX

(Input)

+VS

+VS

YOS

R18

-VS

R5

X OS

-VS

R21 = Rb

R19

R20

Ra

Rb

Rc

R AX

8

5

VX (Offset)

I1

I4

R6

R8

7

RC4200

R7

Multiplier

1

0.1 µF I2

4

2

R9

0.1 µ F

3

6 I3

-VS

R10

R11

Rd

R4

VZ

(Input)

+VS

R12

R13 Z OS

VZ (Offset)

-VS

RO

VO

(Output)

Rao

R18-R21 can be used in place of R9 to help

cancel gain error due to resistor product

mis-match (See Appendix 1).

0.1µ F

R14

R16

R15

+VS

R17 V OS

VO (Offset)

-VS

General

10K ≤ R5 = R13 = R17 ≤ 50K

R7 + R8 ≈ R1 | | Ra | | Raz | | Rao

R6 ≈ R7 (VS/0.05)

R9 = Rb

R10 ≈ 100 x R4

R11 = 20K

R12 = 100K

R14 + R15 ≈ R0 | | Rc

R16 ≈ R15 (VS/0.10)

Example: Two-Quad Divider

V0 = K(VX/VZ), K = k, VREF = +VS = +15V

-10 ≤ VX ≤ +10, therefore ∆VX = 20

0 ≤ VZ ≤ +10, therefore ∆VZ = 20

-10 ≤ V0 ≤ +10, therefore ∆V0 = 20

R0 = 26.7K

R1 = 333K

Rb = 60K

R5, R13, R17 = 10K

R4 = 50K

R7, R15 = 1K

Rc = 37.5K

R8, R11 = 20K

Rd = 300K

R6, R9, R16 = 300K

Ra = 187.5K

R10 = 4.7M

Raz = 31.25

R12 = 100K

Rao = 133K

65-1878

Figure 7. Divider Circuit with Offset Adjustment

8

REV. 1.2.1 6/14/01

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