F2117RBG20V Просмотр технического описания (PDF) - Renesas Electronics

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F2117RBG20V

16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Renesas Electronics 

Section 5 Interrupt Controller ..............................................................................85

5.1 Features................................................................................................................................ 85

5.2 Input/Output Pins ................................................................................................................. 87

5.3 Register Descriptions ........................................................................................................... 88

5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) .............................................. 89

5.3.2 Address Break Control Register (ABRKCR) ......................................................... 91

5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 92

5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 93

5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 96

5.3.6 IRQ Status Registers (ISR16, ISR) ......................................................................... 97

5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR)

Wake-Up Event Interrupt Mask Registers (WUEMR) ........................................... 99

5.3.8 IRQ Sense Port Select Register 16 (ISSR16)

IRQ Sense Port Select Register (ISSR)................................................................. 103

5.3.9 Wake-Up Sense Control Register (WUESCR) Wake-Up Input Interrupt

Status Register (WUESR) Wake-Up Enable Register (WER).............................. 104

5.4 Interrupt Sources................................................................................................................ 105

5.4.1 External Interrupt Sources .................................................................................... 105

5.4.2 Internal Interrupt Sources ..................................................................................... 108

5.5 Interrupt Exception Handling Vector Tables ..................................................................... 108

5.6 Interrupt Control Modes and Interrupt Operation .............................................................. 117

5.6.1 Interrupt Control Mode 0 ...................................................................................... 119

5.6.2 Interrupt Control Mode 1 ...................................................................................... 121

5.6.3 Interrupt Exception Handling Sequence ............................................................... 124

5.6.4 Interrupt Response Times ..................................................................................... 125

5.7 Address Breaks .................................................................................................................. 126

5.7.1 Features................................................................................................................. 126

5.7.2 Block Diagram...................................................................................................... 126

5.7.3 Operation .............................................................................................................. 127

5.7.4 Usage Notes .......................................................................................................... 127

5.8 Usage Notes ....................................................................................................................... 129

5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 129

5.8.2 Instructions for Disabling Interrupts ..................................................................... 130

5.8.3 Interrupts during Execution of EEPMOV Instruction........................................... 130

5.8.4 Vector Address Switching .................................................................................... 130

5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode.................... 131

5.8.6 Noise Canceller Switching.................................................................................... 131

5.8.7 IRQ Status Register (ISR)..................................................................................... 131

Rev. 1.00 Apr. 28, 2008 Page xi of xxvi

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