PA28200CVB120 Просмотр технического описания (PDF) - Intel
Номер в каталоге
Компоненты Описание
производитель
PA28200CVB120 Datasheet PDF : 55 Pages
| |||
E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
4.12 AC Characteristics—Read Only Operations(1)—Extended Temperature
Prod
TBV-80
TBV-80
TBE-120
Symbol
Parameter
VCC
3.3 ± 0.3 V(5)
5 V ± 10%(6)
Unit
Load
50 pF
100 pF
Notes Min
Max
Min
Max
tAVAV
Read Cycle Time
110
80
ns
tAVQV
Address to Output Delay
110
80
ns
tELQV
CE# to Output Delay
2
110
80
ns
tPHQV
RP# to Output Delay
0.8
0.45
µs
tGLQV
OE# to Output Delay
2
65
40
ns
tELQX
CE# to Output in Low Z
3
0
0
ns
tEHQZ
CE# to Output in High Z
3
45
25
ns
tGLQX
OE# to Output in Low Z
3
0
0
ns
tGHQZ
OE# to Output in High Z
3
45
25
ns
tOH
Output Hold from Address, CE#,
3
0
or OE# Change, Whichever
Occurs First
0
ns
tELFL
CE# Low to BYTE# High or Low
3
0
tELFH
0
ns
tAVFL
Address to BYTE# High or Low
3
5
5
ns
tFLQV
BYTE# to Output Delay
3,4
110
80
ns
tFHQV
tFLQZ
BYTE# Low to Output in High Z
3
45
30
ns
tPLPH
Reset Pulse Width
7
150
60
ns
tPLQZ
RP# Low to Output High-Z
150
60
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE–tOE after the falling edge of CE# without impact on tCE.
3. Sampled, but not 100% tested.
4. tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A–1 becomes valid.
5. See Test Configuration (Figure 21), 3.6 V and 3.3 ± 0.3 V Standard Test component values.
6. See Test Configuration (Figure 21), 5 V Standard Test component values.
7. The specification tPLPH is the minimum time that RP# must be held low in order to product a valid reset of the device.
SEE NEW DESIGN RECOMMENDATIONS
49
Share Link: 