PA28200CVB120 Просмотр технического описания (PDF) - Intel

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PA28200CVB120

2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel 

2-MBIT SmartVoltage BOOT BLOCK FAMILY

E

NOTES:

See AC Characteristics—WE#-Controlled Write Operations for notes 1 through 11.

12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where

CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should

be measured relative to the CE# waveform.

1

VIH

ADDRESSES (A)

VIL

VIH

WE# (W)

2

AIN

t AVAV

3

AIN

t AVEH

4

t EHAX

VIL

VIH

t

WLEL

OE# (G)

tEHWH

VIL

VIH

CE# (E)

t EHEL

t EHQV1,2,3,4

VIL

t ELEH

t DVEH

VIH

DATA (D/Q)

VIL

High Z

DIN

6.5V VHH

t PHEL

RP# (P) VIH

t EHDX

DIN

tPHHEH

VIL

VIH

WP# VIL

VPPH 2

VPPH1

V (V)

PP

VPPLK

VIL

t VPEH

NOTES:

1. VCC Power-Up and Standby.

2. Write program or Erase Set-Up Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

5

6

Valid

SRD

DIN

tQVPH

t QVVL

Figure 18. Alternate AC Waveforms for Write Operations (CE#–Controlled Writes)

0530_18

42

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