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PIC16C710T

8-Bit CMOS Microcontrollers with A/D Converter

Microchip Technology 

PIC16C71X

4.2 Data Memory Organization

The data memory is partitioned into two Banks which

contain the General Purpose Registers and the Special

Function Registers. Bit RP0 is the bank select bit.

RP0 (STATUS<5>) = 1 → Bank 1

RP0 (STATUS<5>) = 0 → Bank 0

Each Bank extends up to 7Fh (128 bytes). The lower

locations of each Bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers implemented as

static RAM. Both Bank 0 and Bank 1 contain special

function registers. Some "high use" special function

registers from Bank 0 are mirrored in Bank 1 for code

reduction and quicker access.

4.2.1 GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indi-

rectly through the File Select Register FSR

(Section 4.5).

FIGURE 4-4: PIC16C710/71 REGISTER FILE

MAP

File

Address

00h INDF(1)

01h TMR0

02h

PCL

03h STATUS

04h

FSR

05h PORTA

06h PORTB

07h

08h ADCON0

09h ADRES

0Ah PCLATH

0Bh INTCON

0Ch

General

Purpose

Register

2Fh

30h

INDF(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCON(2)

ADCON1

ADRES

PCLATH

INTCON

General

Purpose

Register

File

Address

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

Mapped

in Bank 0(3)

AFh

B0h

7Fh

Bank 0

FFh

Bank 1

Note 1:

2:

3:

Unimplemented data memory locations, read

as '0'.

Not a physical register.

The PCON register is not implemented on the

PIC16C71.

These locations are unimplemented in Bank 1.

Any access to these locations will access the

corresponding Bank 0 register.

DS30272A-page 12

© 1997 Microchip Technology Inc.

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