MC10E016 MC100E016
Applications Information (continued)
EL01
Q0 –> Q7
LO CE
PE
E016
LSB
CLK TC
CLOCK
PO –> P7
Q0 –> Q7
CE
PE
E016
Q0 –> Q7
CE
PE
E016
CLK TC
EL01
PO –> P7
CLK TC
EL01
PO –> P7
Figure 4. 32-Bit Cascaded E016 Programmable Divider
Q0 –> Q7
CE
PE
E016
MSB
CLK TC
PO –> P7
Figure 4 on the following page shows a typical block
diagram of a 32-bit divider chain. Once again to maximize the
frequency of operation EL01 OR gates were used. For lower
frequency applications a slower OR gate could replace the
EL01. Note that for a 16-bit divider the OR function feeding the
PE (program enable) input CANNOT be replaced by a wire OR
tie as the TC output of the least significant E016 must also feed
the CE input of the most significant E016. If the two TC outputs
were OR tied the cascaded count operation would not operate
properly. Because in the cascaded form the PE feedback is
external and requires external gating, the maximum frequency
of operation will be significantly less than the same operation
in a single device.
Maximizing E016 Count Frequency
The E016 device produces 9 fast transitioning single ended
outputs, thus VCC noise can become significant in situations
where all of the outputs switch simultaneously in the same
direction. This VCC noise can negatively impact the maximum
frequency of operation of the device. Since the device does
not need to have the Q outputs terminated to count properly,
it is recommended that if the outputs are not going to be used
in the rest of the system they should be left unterminated. In
addition, if only a subset of the Q outputs are used in the
system only those outputs should be terminated. Not
terminating the unused outputs will not only cut down the VCC
noise generated but will also save in total system power
dissipation. Following these guidelines will allow designers to
either be more aggressive in their designs or provide them
with an extra margin to the published data book specifications.
MOTOROLA
2–6
ECLinPS and ECLinPS Lite
DL140 — Rev 4