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ST72254G2

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES

STMicroelectronics 

ST72104G, ST72215G, ST72216G, ST72254G

I/O PORTS (Cont’d)

Figure 21. I/O Port General Block Diagram

REG ISTE R

ACCESS

ALTERNATE

OUTPUT

1

0

ALTERNATE

ENABLE

DR

DDR

OR

OR SEL

If implemented

DDR SEL

DR SEL

1

0

EXTERNAL

INTERRUPT

SOURCE (eix)

POLARITY

SELECTION

FROM

OTHER

BITS

VDD

P-BUFFER

(see table below)

PULL-UP

(see table below)

VDD

PULL-UP

CONDITI ON

PAD

N-BUFFER

CMOS

SCHMITT

TRIGG ER

DIODES

(see table below)

ANALOG

INPUT

ALTERNATE

INPUT

Table 6. I/O Port Mode Options

Configuration Mode

Input

Output

Floating with/without Interrupt

Pull-up with/without Interrupt

Push-pull

Open Drain (logic level)

True Open Drain

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Pull -Up

Off

On

Off

NI

P-Buffer

Off

On

Off

NI

Diodes

to VDD

to VSS

On

On

NI (see note)

Note: The diode to VDD is not implemented in the

true open drain pads. A local protection between

the pad and VSS is implemented to protect the de-

vice against positive stress.

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