OM6211U Просмотр технического описания (PDF) - Philips Electronics

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OM6211U

48×84 dot matrix LCD driver

Philips Electronics 

Philips Semiconductors

48 × 84 dot matrix LCD driver

Product specification

OM6211

18.2 VPR default value

The second feature is an OTP factory default setting for VPR. This is an 8-bit value from which the VPR register can be

loaded using the ‘Load factory default’ command. The idea of this feature is to make it unnecessary for the set maker to

specify the VPR value. The factory default may be overridden by the set maker in the normal fashion using the ‘Set VPR’

commands.

handbook, full pagewidth

interface data

OTP VPR default register, 8-bit value

load VPR via the interface

+

VPR register: 8-bit value

load VPR from an OTP

default register.

MGU288

Fig.21 Load VPR register: default or specified via interface.

18.3 Seal bit

The module maker programming is performed in a special

mode: the calibration mode (CALMM). This mode is

entered via a special interface command, CALMM.

To prevent wrongful programming, a seal bit has been

implemented which prevents the device from entering the

calibration mode. This seal bit, once programmed, cannot

be reversed, thus further changes in programmed values

are not possible. However, it is possible to disable all

programmed values by not applying the ‘Enable OTP’

command.

Applying the programming voltages when not in CALMM

mode will have no effect on the programmed values.

Table 10 Seal bit definition

SEAL BIT

0

1

ACTION

possible to enter calibration mode

calibration mode disabled

18.4 OTP architecture

The OTP circuitry in the OM6211 contains 14 bits of data:

5 for VLCD calibration, 8 for VPR default and 1 seal bit. The

circuitry for 1-bit is called an OTP slice, thus there are

14 OTP slices.

Each OTP slice consists of 2 main parts: the OTP cell

(a non-volatile memory cell) and the shift register cell

(a flip-flop). The OTP cells are only accessible through

their shift register cells: on the one hand both reading from

and writing to the OTP cells is performed with the shift

register cells, on the other hand only the shift register cells

are visible to the rest of the circuit. The basic OTP

architecture is shown in Fig.22.

This OTP architecture enables the following operations:

1. Reading data from the OTP cells. The content of the

non-volatile OTP cells is transferred to the shift

register where it may affect the OM6211 operation

(provided it has been enabled by the ‘Enable OTP’

command).

2. Writing data to the OTP cells. Firstly, all 14 bits of data

are shifted into the shift register via the serial interface.

The content of the shift register is then transferred to

the OTP cells (there are some limitations related to

storing data in these cells, see Section 18.7).

3. Checking calibration without writing to the OTP cells.

Shifting data into the shift register allows the effects on

the VLCD voltage to be observed.

2002 Jan 17

29

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