Philips Semiconductors
Video analog input interface
Product specification
TDA8708A
Notes
1. 0 dB is obtained at the AGC amplifier when applying Vi(p-p) = 1.33 V.
2. The output current at pin 19 should not exceed 1 mA. The load impedance RL should be referenced to VCCA and
defined as:
a) AC impedance ≥1 kΩ and the DC impedance >2.7 kΩ.
b) The load impedance should be coupled directly to the output of the amplifier so that the DC voltage supplied by
the clamp is not disturbed.
3. Control mode 2 is selected.
4. Signal-to-noise ratio measured with 5 MHz bandwidth:
N-S-- = 20 log V-----AV---N-A--O--N-U--O--T--UY----T-(-R-C--M--(--pS---–-n---op--i-)s--e---) at B = 5 MHz.
5. The voltage ratio is expressed as:
SVRR1 = 20 log∆---V--V--C--C-C--C--A--A- × ∆---G--G--- for VI = 1 V (p-p), gain at 100 kHz = 1 and 1 V supply variation.
6. It is recommended that the rise and fall times of the clock are ≥2 ns. In addition, a ‘good layout’ for the digital and
analog grounds is recommended.
7. These measurements are realized on analog signals after a digital-to-analog conversion (TDA8702 is used).
8. The supply voltage rejection is the relative variation of the analog signal (full-scale signal at input) for 1 V of supply
variation:
SVRR2 = -∆-----(--V----I---(--0--0---)---–-----V----I--(--F---F-∆--)--V-)---C-+---C---(A---V----I--(--0---0--)----–-----V----I--(--F---F---)--)---
9. Full-scale sine wave (fi = 4.4 MHz; fclk = 27 MHz).
June 1994
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