NCP1255BSN65T1G Просмотр технического описания (PDF) - ON Semiconductor

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NCP1255BSN65T1G

Current-Mode PWM Controller for Off-line Power Supplies featuring Peak Power Excursion

ON Semiconductor 

NCP1255

This calculation is purely theoretical, considering a

constant charging current. In reality, the take over time can

be shorter (or longer!) and it can lead to a reduction of the

Vcc capacitor. This brings a decrease in the charging current

and an increase of the start−up resistor, for the benefit of

standby power. Laboratory experiments on the prototype are

thus mandatory to fine tune the converter. If we chose the

400−kW resistor as suggested by Equation 4, the dissipated

power at high line amounts to:

ǒ Ǔ PRstartup,max +

Vac,peak 2

4Rstart−up

+

230

4

Ǹ2 2

400 k

+

105 k

1.6 Meg

+

66

mW

(eq. 5)

Now that the first Vcc capacitor has been selected, we must

ensure that the self−supply does not disappear when in

no−load conditions. In this mode, the skip−cycle can be so

deep that refreshing pulses are likely to be widely spaced,

inducing a large ripple on the Vcc capacitor. If this ripple is

too large, chances exist to touch the VCCmin and reset the

controller into a new start−up sequence. A solution is to

grow this capacitor but it will obviously be detrimental to the

start−up time. The option offered in Figure 3 elegantly

solves this potential issue by adding an extra capacitor on the

auxiliary winding. However, this component is separated

from the Vcc pin via a simple diode. You therefore have the

ability to grow this capacitor as you need to ensure the

self−supply of the controller without affecting the start−up

time and standby power.

Triggering the SCR

The latched−state of the NCP1255 is maintained via an

internal thyristor (SCR). When the voltage on pin 1 exceeds

the latch voltage for four consecutive clock cycles, the SCR

is fired and immediately stops the output pulses. The same

SCR is fired when an OVP is sensed on the Vcc pin. When

this happens, all pulses are stopped and Vcc is discharged to

a fix level of 7 V typically: the circuit is latched and the

converter no longer delivers pulses. To maintain the

latched−state, a permanent current must be injected in the

part. If too low of a current, the part de−latches and the

converter resumes operation. This current is characterized to

32 mA as a minimum but we recommend including a design

margin and select a value around 60 mA. The test is to latch

the part and reduce the input voltage until it de−latches. If

you de−latch at Vin = 70 V rms for a minimum voltage of

85 V rms, you are fine. If it precociously recovers, you will

have to increase the start−up current, unfortunately to the

detriment of standby power.

The most sensitive configuration is actually that of the

half−wave connection proposed in Figure 3. As the current

disappears 5 ms for a 10−ms period (50−Hz input source),

the latch can potentially open at low line. If you really reduce

the start−up current for a low standby power design, you

must ensure enough current in the SCR in case of a faulty

event. An alternate connection to the above is shown below

(Figure 4):

1 Meg

1 Meg

N

Vcc

L1

Figure 4. The full−wave connection ensures latch

current continuity as well as a X2−discharge path.

In this case, the current is no longer made of 5−ms “holes”

and the part can be maintained at a low input voltage.

Experiments show that these 2−MW resistor help to maintain

the latch down to less than 50 V rms, giving an excellent

design margin. Standby power with this approach was also

improved compared to Figure 3 solution. Please note that

these resistors also ensure the discharge of the X2−capacitor

up to a 0.47 mF type.

The de−latch of the SCR occurs when a) the injected

current in the Vcc pin falls below the minimum stated in the

data−sheet (32 mA at room temp). When the start−up

resistors are connected as suggested by Figure 3 the reset

time when unplugging the converter is extremely short,

typically below the second.

Internal Over Power Protection

There are several known ways to implement Over Power

Protection (OPP), all suffering from particular problems.

These problems range from the added consumption burden

on the converter or the skip−cycle disturbance brought by

the current−sense offset. A way to reduce the power

capability at high line is to capitalize on the negative voltage

swing present on the auxiliary diode anode. During the

turn−on time, this point dips to −NVin, N being the turns ratio

between the primary winding and the auxiliary winding. The

negative plateau observed on Figure 5 will have an

amplitude depending on the input voltage. The idea

implemented in this chip is to sum a portion of this negative

swing with the 0.8−V internal reference level. For instance,

if the voltage swings down to −150 mV during the on time,

then the internal peak current set point will be fixed to

0.8−0.150 = 650 mV. The adopted principle appears in

Figure 6 and shows how the final peak current set point is

constructed.

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