MT9072AB Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT9072AB

Octal T1/E1/J1 Framer

Zarlink Semiconductor Inc 

MT9072

Data Sheet

AC Electrical Characteristics - Receive Basic Frame and E4o Timing

Characteristics

Sym. Min. Typ. Max. Units

Test Conditions

1 Basic Frame Output Delay

2 Clock Delay

3 E4o Clock High Width

3 E4o Clock Low Width

tBD

30

tCD

tE4HW 50

tE4LW 25

115 ns 150 pF load on RxBF

55

ns 150 pF load on RxDLC

200 ns 150 pF load on RxDLC

75

ns 150 pF load on RxDLC

RXDL

PCM 30

Bit Cells

Timeslot 31

Bit 8

Timeslot 0

Bit 1

E2i

Input

VT

tE4HW

tE4LW

tCD

tCD

E4o - Note 1

(RxDLC Pin)

Output

RxBF

(Output)

VT

tBD

t

BD

VT

Note 1 - The E4o signal is output at the RxDLC Pin when the E4CK control bit (address Y08) is set to one.

Note 2 - The PCM Timeslots are referred to RXDL Output which is delayed 4 bits from the RPOS/RNEG input.

Note3- The E4o Clock(RXDLC Output) is not a 50% duty cycle clock, it will be low for 25 % and high for 75% of the

4.096 MHz clock

Figure 67 - Receive Basic Frame and E4o Timing

266

Zarlink Semiconductor Inc.

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