MT46H16M32LF Просмотр технического описания (PDF) - Micron Technology

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MT46H16M32LF

Mobile Low-Power DDR SDRAM

Micron Technology 

512Mb: x16, x32 Mobile LPDDR SDRAM

WRITE Operation

Figure 42: WRITE-to-PRECHARGE – Interrupting

CK#

CK

Command1

T0

WRITE2

Address

Bank a,

Col b

tDQSS (NOM)

DQS5

tDQSS

DQ6

DM

T1 T1n T2

T2n T3 T3n T4

T4n T5

NOP

NOP

NOP

tWR4

PRE3

(aBoarnakll)

NOP

DbIN

bD+IN1

tDQSS (MIN)

DQS5

DQ6

DM

tDQSS

DbIN

bD+IN1

T6

NOP

tDQSS (MAX)

DQS5

DQ6

DM

tDQSS

DbIN

bD+IN1

Don’t Care

Transitioning Data

Notes:

1. An interrupted burst of 8 is shown; two data elements are written.

2. A10 is LOW with the WRITE command (auto precharge is disabled).

3. PRE = PRECHARGE.

4. tWR is referenced from the first positive CK edge after the last data-in pair.

5. DQS is required at T4 and T4n to register DM.

6. DINb = data-in for column b.

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN

81

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