MSM5416258A-45TS-K Просмотр технического описания (PDF) - Oki Electric Industry

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MSM5416258A-45TS-K

262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

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¡ Semiconductor

MSM5416258A

Notes: 1. All voltages are referenced to VSS.

2. This parameter is dependent upon the cycle rate.

3. This parameter is dependent upon the output loading. Specified values are obtained

with the output open.

4. An initial pause of 200 ms is required after power-up, followed by any 8 RAS cycles.

(Example : RAS-only-refresh) before proper device operation is achieved. In case of

using internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS

cycles are required.

5. The AC characteristics assume tT = 5 ns.

6. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals.

Also, transition times are measured between VIH and VIL.

7. Data outputs are measured with a load of 50 pF. DOUT reference levels: VOH/VOL =

2.0 V/1.4 V. Note that VOL is defined as 1.4 V when VSS* pins, pin 13 and pin 32, were

open. The data output measurements under VOH/VOL = 2.0 V/0.8 V are guaranteed

when VSS* pins, pin 13 and pin 32, were connected to GND.

8. tREZ (Max.), tOFF (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the

outputs achieve the open circuit condition and are not referenced to output voltage

levels. This parameter is sampled and not 100% tested.

9. Either tRCH or tRRH must be satisfied for a read cycle.

10. These parameters are referenced to CAS leading edge of early write cycles and to WE

leading edge in OE-controlled write cycles and read-modify-write cycles.

11. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included

in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), the cycle is an

early write cycle and the data out pins will remain open circuit throughout the entire

cycle. If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.), the cycle is

a read-modify-write cycle and the data out will contain data read from the selected cell.

If neither of the above sets of conditions is satisfied, the condition of the data out is

indeterminate.

12. Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met.

tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified

tRCD (Max.) limit, then access time is controlled by tCAC.

13. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.

tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified

tRAD (Max.) limit, then access time is controlled by tAA.

14. Input levels at the AC testing are 3.0 V/0 V.

15. Addresses (A0 - A8) may be changed two times or less while RAS = VIL.

16. Addresses (A0 - A8) may be changed once or less while CAS = VIH and RAS = VIL.

17. This is guaranteed by design. (tCOH = tCAC - output transition time). This parameter is

not 100% tested.

18. This parameter is dependent upon the number of address transitions. Specified values

are measured with a maximum of two transitions per address cycle in Fast Page Mode.

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