MSC2313258A-60DS2 Просмотр технического описания (PDF) - Oki Electric Industry

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MSC2313258A-60DS2

1,048,576-Word x 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO

Oki Electric Industry 

MSC2313258A-xxBS2/DS2

¡ Semiconductor

Notes:

1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight

initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device

operation is achieved.

2. The AC characteristics assume tT = 5 ns.

3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.

Transition times (tT) are measured between VIH and VIL.

4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.

5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.

tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified

tRCD (Max.) limit, access time is controlled by tCAC.

6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.

tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified

tRAD (Max.) limit, access time is controlled by tAA.

7. tCEZ (Max.), tREZ (Max.) and tWEZ (Max.) define the time at which the output achieves

the open circuit condition and are not referenced to output voltage levels.

8. tCEZ and tREZ must be satisfied for open circuit condition.

9. tRCH or tRRH must be satisfied for a read cycle.

See ADDENDUM H for AC Timing Waveforms

60

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