MPC950FA Просмотр технического описания (PDF) - Motorola => Freescale
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MPC950FA Datasheet PDF : 13 Pages
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MPC950 MPC951
The oscillator circuit is a series resonant circuit as
opposed to the more common parallel resonant circuit, this
eliminates the need for large on–board capacitors. Because
the design is a series resonant design for the optimum
frequency accuracy a series resonant crystal should be used
(see specification table below). Unfortunately most off the
shelf crystals are characterized in a parallel resonant mode.
However a parallel resonant crystal is physically no different
than a series resonant crystal, a parallel resonant crystal is
simply a crystal which has been characterized in its parallel
resonant mode. Therefore in the majority of cases a parallel
specified crystal can be used with the MPC950/951 with just
a minor frequency error due to the actual series resonant
frequency of the parallel resonant specified crystal. Typically
a parallel specified crystal used in a series resonant mode
will exhibit an oscillatory frequency a few hundred ppm lower
than the specified value. For most processor
implementations a few hundred ppm translates into kHz
inaccuracies, a level which does not represent a major issue.
Table 3. Crystal Specifications
Parameter
Crystal Cut
Resonance
Frequency Tolerance
Frequency/Temperature Stability
Operating Range
Shunt Capacitance
Equivalent Series Resistance (ESR)
Correlation Drive Level
Aging
Value
Fundamental AT Cut
Series Resonance*
±75ppm at 25°C
±150ppm 0 to 70°C
0 to 70°C
5–7pF
50 to 80Ω Max
100µW
5ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
The MPC950/951 is a clock driver which was designed to
generate outputs with programmable frequency relationships
and not a synthesizer with a fixed input frequency. As a result
the crystal input frequency is a function of the desired output
frequency. For a design which utilizes the external feedback
to the PLL the selection of the crystal frequency is straight
forward; simply chose a crystal which is equal in frequency to
the fed back signal. To determine the crystal required to
produce the desired output frequency for an application
which utilizes internal feedback the block diagram of
Figure 11 should be used. The P and the M values for the
MPC950/951 are also included in Figure 11. The M values
can be found in the configuration tables included in this
applications section.
fref
VCO
Phase
Detector LPF
÷P
÷N
Qn
÷m
+ + fref
fVCO
m
,
fVCO
fQn · N · P
N + fref
fQn · N · P
m
m = 8 (FBsel = ‘1’), 16(FBsel = ‘0’)
P=1
Figure 11. PLL Block Diagram
For the MPC950/951 clock driver, the following will provide
an example of how to determine the crystal frequency
required for a given design.
Given:
Qa = 160MHz
Qb = 80MHz
Qc = 40MHz
Qd = 40MHz
FBSel = ‘0’
+ fref
fQn · N · P
m
From Table 3
fQd = VCO/8 then N = 8 OR fQa = VCO/2 then N = 2
From Figure 11
m = 16 and P = 1
+ + + fref
40 · 8 · 1
16
20MHz OR 160 · 2 · 1
16
20MHz
Driving Transmission Lines
The MPC950/951 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
MOTOROLA
10
TIMING SOLUTIONS
BR1333 — Rev 6
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