MPC9352 Просмотр технического описания (PDF) - Motorola => Freescale
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MPC9352 Datasheet PDF : 16 Pages
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MPC9352
Freescale Semiconductor, Inc.
APPLICATIONS INFORMATION
Programming the MPC9352
The MPC9352 supports output clock frequencies from
16.67 to 200 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2
as well as 2:3, 3:1 and 2:1. Table 1 illustrates the various
output configurations and frequency ratios supported by the
MPC9352. See also Table 9, Table 10 and Figure 3 to Figure
6 for further reference. A ÷2 output divider cannot be used for
feedback.
Table 9: MPC9352 Example Configuration (F_RANGE = 0)
PLL Feedback
VCO ÷ 4b
frefa [MHz]
50-100
FSELA FSELB FSELC QA[0:4]:fref ratio
0
0
0
fref (50-100 MHz)
0
0
1
fref (50-100 MHz)
1
0
0
fref ⋅ 2÷3 (33-66 MHz)
1
0
1
fref ⋅ 2÷3 (33-66 MHz)
VCO ÷ 6c
33.3-66.67
1
0
0
fref
(33-66 MHz)
1
0
1
fref
(33-66 MHz)
1
1
0
fref
(33-66 MHz)
1
1
1
fref
a. fref is the input clock reference frequency (CCLK)
b. QAx connected to FB_IN and FSELA=0
c. QAx connected to FB_IN and FSELA=1
(33-66 MHz)
QB[0:3]:fref ratio
fref (50-100 MHz)
fref (50-100 MHz)
fref (50-100 MHz)
fref (50-100 MHz)
fref ⋅3÷2 (50-100 MHz)
fref ⋅3÷2 (50-100 MHz)
fref ⋅ 3 (100-200 MHz)
fref ⋅ 3 (100-200 MHz)
QC[0:1]:fref ratio
fref ⋅ 2 (100-200 MHz)
fref (50-100 MHz)
fref ⋅ 2 (100-200 MHz)
fref (50-100 MHz)
fref ⋅ 3 (100-200 MHz)
fref ⋅3÷2 (50-100 MHz)
fref ⋅ 3 (100-200 MHz)
fref ⋅3÷2 (50-100 MHz)
Table 10: MPC9352 Example Configurations (F_RANGE = 1)
PLL Feedback
VCO ÷ 8b
frefa [MHz]
25-50
FSELA FSELB FSELC QA[0:4]:fref ratio
0
0
0
fref
(25-50 MHz)
0
0
1
fref
(25-50 MHz)
1
0
0
fref ⋅2÷3 (16-33 MHz)
1
0
1
fref ⋅2÷3 (16-33 MHz)
VCO ÷ 12c
16.67-33.3
1
0
0
fref
(16-33 MHz)
1
0
1
fref
(16-33 MHz)
1
1
0
fref
(16-33 MHz)
1
1
1
fref
a. fref is the input clock reference frequency (CCLK)
b. QAx connected to FB_IN and FSELA=0
c. QAx connected to FB_IN and FSELA=1
(16-33 MHz)
QB[0:3]:fref ratio
fref
(25-50 MHz)
fref
(25-50 MHz)
fref
(25-50 MHz)
fref
(25-50 MHz)
fref ⋅3÷2 (25-50 MHz)
fref ⋅3÷2 (25-50 MHz)
fref ⋅ 3 (50-100 MHz)
fref ⋅ 3 (50-100 MHz)
QC[0:1]:fref ratio
fref ⋅ 2 (50-100 MHz)
fref
(25-50 MHz)
fref ⋅ 2 (50-100 MHz)
fref
(25-50 MHz)
fref ⋅ 3 (50-100 MHz)
fref ⋅3÷2 (25-50 MHz)
fref ⋅ 3 (50-100 MHz)
fref ⋅3÷2 (25-50 MHz)
MOTOROLA
8
For More Information On This Product,
Go to: www.freescale.com
TIMING SOLUTIONS
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