MPC9350 Просмотр технического описания (PDF) - Motorola => Freescale

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производитель

MPC9350

Low Voltage PLL Clock Driver

Motorola => Freescale 

Freescale Semiconductor, Inc.

PULSE

W GENERATOR

Z = 50

ZO = 50Ω

MPC9350 DUT

ZO = 50Ω

RT = 50Ω

RT = 50Ω

VTT

VTT

Figure 7. TCLK MPC9350 AC test reference for Vcc = 3.3V and Vcc = 2.5V

MPC9350

B VCC

VCC 2

GND

B VCC

VCC 2

GND

tSK(O)

The pin–to–pin skew is defined as the worst case difference in propagation

delay between any similar delay path within a single device

Figure 8. Output–to–output Skew tSK(O)

B VCC

VCC 2

GND

tP

T0

DC = tP/T0 x 100%

The time from the PLL controlled edge to the non controlled edge, divided

by the time between PLL controlled edges, expressed as a percentage

Figure 9. Output Duty Cycle (DC)

VCC=3.3V VCC=2.5V

2.4

1.8V

0.55

0.6V

tF

tR

The time from the maximum low level voltage to minimum high level of a

clock signal, expressed in ns

Figure 10. Transition Time Test Reference

TN TN+1

TJIT(CC) = |TN–TN+1|

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

Figure 11. Cycle–to–cycle Jitter

TJIT(P) = |TN–1/f0|

T0

The deviation in cycle time of a signal with respect to the ideal period over

a random sample of cycles

Figure 12. Period Jitter

TIMING SOLUTIONS

For More Informa9tion On This Product,

Go to: www.freescale.com

MOTOROLA

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