MPC9330FA Просмотр технического описания (PDF) - Motorola => Freescale

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Компоненты Описание

производитель

MPC9330FA

3.3V/2.5V 1:6 LVCMOS PLL CLOCK GENERATOR

Motorola => Freescale 

MPC9330

APPLICATIONS INFORMATION

Output power down (PWR_DN) timing diagram

VCO÷2

VCO÷4

PWR_DWN

QAx (÷2)

QBx (÷4)

QBCx (÷6)

Output clock stop (CLK_STOP) timing diagram

QAx (÷2)

QBx (÷4)

QCx (÷6)

CLK_STOP0

CLK_STOP1

QAx (÷2)

QBx (÷4)

QCx (÷6)

Programming the MPC9330

The MPC9330 supports output clock frequencies from

6.67 to 200 MHz. Different feedback and output divider

configurations can be used to achieve the desired input to

output frequency relationship. The feedback frequency and

divider should be used to situate the VCO in the frequency

lock range between 200 and 400 MHz for stable and optimal

operation. The FSELA, FSELB, FSELC and PWR_DN pins

select the desired output clock frequencies. Possible

frequency ratios of the reference clock input to the outputs

are 1:4, 1:3, 1:2, 1:1, 2:3, 4:3 and 3:2. Tables 10 through 12

illustrate the various output configurations and frequency

ratios supported by the MPC9330.

TIMING SOLUTIONS

7

MOTOROLA

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