ML2652 Просмотр технического описания (PDF) - Micro Linear Corporation
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ML2652 Datasheet PDF : 23 Pages
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ML2652/ML2653
FUNCTIONAL DESCRIPTION (Continued)
The receive squelch circuit determines when data on
incoming Rx+, Rx– is valid. The receive squelch is
considered “on” when the data is deemed to be invalid,
and the receive squelch is considered “off” when data is
determined to be valid.
The input signal must meet the following criteria in order
to turn receive squelch off and be recognized as valid
data:
1. The input signal must exceed the receive squelch
on level. When this occurs, a 400ns squelch interval
timer is started.
2. During the 400ns squelch interval, the input signal
must go from one squelch threshold to the opposite
polarity squelch threshold in less than 127ns.
3. During the 400ns squelch interval, the input signal
has to make less than 9 squelch threshold to opposite
polarity squelch threshold crossings.
When the receive squelch is turned off, the receive
squelch off level is reduced to 2/3 of receive squelch on
level.
The receive squelch will be turned back on if either the
incoming data peaks go below the receive squelch off
level for 400ns or the start of idle (SOI) pulse is detected.
The receive squelch on level can be digitally programmed
for one of two possible levels by using the RSL pin. When
RSL = 1, the squelch on level complies with the IEEE
802.3i–1990 specification. When RSL = 0, the receive
squelch on level is lowered in order to accommodate
greater receive attenuation and consequently longer
twisted pair cable lengths. The receive squelch on level
can be programmed as follows:
RECEIVE SQUELCH ON LEVEL
RSL
Application
Min Typ Max
1
10BASE-T
300
585mV
0
Long Distance
200
390mV
The RCV pin is an output that indicates receive activity.
The pin consists of an open drain output with an internal
pull-up resistor and can drive an LED from VCC or another
digital input. In order to make an LED visible, RCV has an
internal blinker circuit that generates a 100ms blink (50ms
high, 50ms low) that is triggered when reception starts. At
the completion of the 100ms blink period, if reception is
in progress, another 100ms blink is generated.
The manchester decoder receives data from either the
twisted pair interface (as described above) or the AUI
(described in AUI section).
The manchester decoder is responsible for recovering
clock and data from the incoming receive bit stream.
18
Clock and data recovery is accomplished by a digital PLL
which can lock on the incoming bit stream in less than
1.6µs.
The clock (RxC) and NRZ data (RxD) are then output to
the external world via the controller interface.
SOI
A start of idle (SOI) pulse is sent at the end of transmission in
order to signal to all receivers that transmission has ended
and the idle period begins. Thus, the transmit section has an
SOI generator and the receive section has an SOI detector.
The transmit SOI pulse generator inserts an SOI pulse at the
end of each transmission. The SOI pulse is typically a 250ns
positive pulse inserted after the last positive data transition.
Depending on the data pattern, the positive data transition
could occur either in the middle or at the end of the last bit
cell. So the actual width of the transmitted SOI pulse can
vary from 250–300ns, typically.
The receive SOI detector senses the SOI pulse using the zero
crossing comparator. When the SOI pulse is detected, the
receiver signals to the controller that receive data is no
longer valid and turns the receive squelch on.
LINK PULSE
During the idle period, link pulses are sent by the transmitter
and detected by the receiver so that the integrity of the
twisted pair link can be continuously monitored. Thus, the
transmit section has a link pulse generator, and the receiver
has a link pulse detector.
The transmit link pulse generator transmits a 100ns wide
positive pulse (Tx+ high, Tx– low) every 16 ±8ms.
IEEE 802.3i–1990 Section 14 requires the link pulse to be
shaped to meet a template when passed or not passed
through the twisted pair line model. The transmit waveform
generator takes the link pulse and generates the waveform
on TX± when passed or not passed through the twisted pair
line model.
The receiver monitors the receive input to determine if the
link pulses are present. When the device is in the link pulse
pass state, normal packet transmission and reception can
occur. All link pulses less than 2–7ms apart are ignored
while in the link pass state. If no link pulses or receive
packets are detected for a period of 50–150ms, the device
goes into the link pulse fail state.
When the device is in the link pulse fail state, reception is
inhibited and the transmitter is placed in the idle state (no
data transmission but link pulses are still transmitted). In
order for the device to exit the link pulse fail state, one
complete packet or 4 consecutive link pulses must be
detected, and transmit and receive must be idle.
Consecutive link pulses are defined as pulses that occur
within 25–150ms of each other. If the link pulses occur
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