MH16S64AMA-12 Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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производитель

MH16S64AMA-12

1073741824-BIT (16777216 - WORD BY 64-BIT) SynchronousDRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

BURST INTERRUPTION

[ Read Interrupted by Read ]

Burst read option can be interrupted by new read of the same or the other bank.

MH16S64AMA allows random column access. READ to READ interval is minimum 1 CK

Read Interrupted by Read (BL=4, CL=3)

CK

Command

READ READ

READ

READ

A0-9,11

Yi Yj

Yk

Yl

A10

00

0

0

BA0,1

00

1

0

DQ

Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3

[ Read Interrupted by Write ]

Burst read operation can be interrupted by write of the same or the other bank. Random

column access is allowed. In this case, the DQ should be controlled adequately by using the

DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after

WRITE assertion.

Read Interrupted by Write (BL=4, CL=3)

CK

Command

READ

Write

A0-9,11

Yi

Yj

A10

0

0

BA0,1

0

0

DQMB0-7

Q

Qai0

D

Daj0 Daj1 Daj2 Daj3

MIT-DS-0127-0.0

DQM control

MITSUBISHI

ELECTRIC

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Write control

4. Mar.1997

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