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33927

Three-Phase Field Effect Transistor Pre-Driver

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 8.0V ≤ VPWR = VBAT ≤ 40V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SPI INTERFACE TIMING

Maximum Frequency of SPI Operation

fOP

–

5.0

MHz

Internal Time Base

Internal Time Base drift from value at 25°C (44)

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (44)

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (44)

SI to Falling Edge of SCLK (Required Setup Time) (44)

Falling Edge of SCLK to SI (Required Setup Time) (44)

SI, CS, SCLK Signal Rise Time (44), (45)

SI, CS, SCLK Signal Fall Time (44), (45)

Time from Falling Edge of CS to SO Low Impedance (44), (46)

Time from Rising Edge of CS to SO High Impedance (44), (47)

Time from Rising Edge of SCLK to SO Data Valid (44), (48)

Time from Rising Edge of CS to Falling Edge of the next CS (44)

fTB

13

17

25

MHz

TCTB

-5

–

5

%

tLEAD

100

–

–

ns

tLAG

100

–

–

ns

tSISU

25

–

–

ns

tSIHOLD

25

–

–

ns

tRSI

–

5.0

–

ns

tFSI

–

5.0

–

ns

tSOEN

–

55

100

ns

tSODIS

–

100

125

ns

tVALID

–

55

100

ns

tDT

200

–

–

ns

Notes

44. This parameter is guaranteed by design, not production tested.

45. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

46. Time required for valid output status data to be available on SO pin.

47. Time required for output states data to be terminated at SO pin.

48. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

33927

16

Analog Integrated Circuit Device Data

Freescale Semiconductor

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