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MC145170D1

PLL Frequency Synthesizer with Serial Interface

Motorola => Freescale 

If desired, an external clock source can be ac coupled to

OSCin. A 0.01 µF coupling capacitor is used for measure-

ment purposes and is the minimum size recommended for

applications. An external feedback resistor of approximately

10 MΩ is required across the OSCin and OSCout pins in

the ac–coupled case (see Figure 8). OSCout is an internal

node on the device and should not be used to drive any loads

(i.e., OSCout is unbuffered). However, the buffered REFout

is available to drive external loads.

The external signal level must be at least 1 V p–p; the

maximum frequencies are given in the Loop Specifications

table. These maximum frequencies apply for R Counter

divide ratios as indicated in the table. For very small ratios,

the maximum frequency is limited to the divide ratio times

2 MHz. (Reason: the phase/frequency detectors are limited

to a maximum input frequency of 2 MHz.)

If an external source is available which swings rail–to–rail

(VDD to VSS), then dc coupling can be used. In the dc–

coupled case, no external feedback resistor is needed.

OSCout must be a No Connect to avoid loading an internal

node on the device, as noted above. For frequencies below

1 MHz, dc coupling must be used. The R counter is a static

counter and may be operated down to dc. However, wave

shaping by a CMOS buffer may be required to ensure fast

rise and fall times into the OSCin pin. See Figure 22.

Each rising edge on the OSCin pin causes the R counter to

decrement by one.

REFout

Reference Frequency Output (Pin 3)

This output is the buffered output of the crystal–generated

reference frequency or externally provided reference source.

This output may be enabled, disabled, or scaled via bits in

the C register (see Figure 14).

REFout can be used to drive a microprocessor clock input,

thereby saving a crystal. Upon power up, the on–chip

power–on–initialize circuit forces REFout to the OSCin

divided–by–8 mode.

REFout is capable of operation to 10 MHz; see the Loop

Specifications table. Therefore, divide values for the refer-

ence divider are restricted to two or higher for OSCin fre-

quencies above 10 MHz.

If unused, the pin should be floated and should be disabled

via the C register to minimize dynamic power consumption

and electromagnetic interference (EMI).

COUNTER OUTPUT PINS

fR

R Counter Output (Pin 9)

This signal is the buffered output of the 15–stage R count-

er. fR can be enabled or disabled via the C register (pat-

ented). The output is disabled (static low logic level) upon

power up. If unused, the output should be left disabled and

unconnected to minimize interference with external circuitry.

The fR signal can be used to verify the R counter’s divide

ratio. This ratio extends from 5 to 32,767 and is determined

by the binary value loaded into the R register. Also, direct

access to the phase detector via the OSCin pin is allowed by

choosing a divide value of 1 (see Figure 15). The maximum

frequency which the phase detectors operate is 2 MHz.

Therefore, the frequency of fR must not exceed 2 MHz.

When activated, the fR signal appears as normally low and

pulses high.

MOTOROLA

fV

N Counter Output (Pin 10)

This signal is the buffered output of the 16–stage N count-

er. fV can be enabled or disabled via the C register (pat-

ented). The output is disabled (static low logic level) upon

power up. If unused, the output should be left disabled and

unconnected to minimize interference with external circuitry.

The fV signal can be used to verify the N counter’s divide

ratio. This ratio extends from 40 to 65,535 and is determined

by the binary value loaded into the N register. The maximum

frequency which the phase detectors operate is 2 MHz.

Therefore, the frequency of fV must not exceed 2 MHz.

When activated, the fV signal appears as normally low and

pulses high.

LOOP PINS

fin

Frequency Input (Pin 4)

This pin is a frequency input from the VCO. This pin feeds

the on–chip amplifier which drives the N counter. This signal

is normally sourced from an external voltage–controlled os-

cillator (VCO), and is ac–coupled into fin. A 100 pF coupling

capacitor is used for measurement purposes and is the mini-

mum size recommended for applications (see Figure 7). The

frequency capability of this input is dependent on the supply

voltage as listed in the Loop Specifications table. For small

divide ratios, the maximum frequency is limited to the divide

ratio times 2 MHz. (Reason: the phase/frequency detectors

are limited to a maximum frequency of 2 MHz.)

For signals which swing from at least the VIL to VIH levels

listed in the Electrical Characteristics table, dc coupling

may be used. Also, for low frequency signals (less than the

minimum frequencies shown in the Loop Specifications

table), dc coupling is a requirement. The N counter is a static

counter and may be operated down to dc. However, wave

shaping by a CMOS buffer may be required to ensure fast

rise and fall times into the fin pin. See Figure 22.

Each rising edge on the fin pin causes the N counter to

decrement by 1.

PDout

Single–Ended Phase/Frequency Detector Output

(Pin 13)

This is a three–state output for use as a loop error signal

when combined with an external low–pass filter. Through use

of a Motorola patented technique, the detector’s dead zone

has been eliminated. Therefore, the phase/frequency detec-

tor is characterized by a linear transfer function. The opera-

tion of the phase/frequency detector is described below and

is shown in Figure 17.

POL bit (C7) in the C register = low (see Figure 14)

Frequency of fV > fR or Phase of fV Leading fR: negative

pulses from high impedance

Frequency of fV < fR or Phase of fV Lagging fR: positive

pulses from high impedance

Frequency and Phase of fV = fR: essentially high–impe–

dance state; voltage at pin determined by loop filter

POL bit (C7) = high

Frequency of fV > fR or Phase of fV Leading fR: positive

pulses from high impedance

Frequency of fV < fR or Phase of fV Lagging fR: negative

pulses from high impedance

Frequency and Phase of fV = fR: essentially high–impe–

dance state; voltage at pin determined by loop filter

MC145170–1

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