MB90098A Просмотр технического описания (PDF) - Fujitsu

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Компоненты Описание

производитель

MB90098A

On-Screen Display Controller

Fujitsu 

MB90098A

s PIN DESCRIPTIONS

Pin Pin no.

DCLKI

5

DCLKO 22

HSYNC 10

VSYNC 11

I/O

Input

Output

Input

Input

DISP

12

Input

DA3

25

DA2

DA1

26

27

Output

DA0

28

VOBA

24

Output

DB3

17

DB2

18

DB1

19

DB0

20

VOBB

16

Output

Output

BUSY

15

Output

CS

1

SIN

2

SCLK

3

RESET

13

TEST

14

VDD

7, 9, 21

VSS

4, 6, 23

TCLKI

8

Input

Input

Input

Input

Input





Input

Circuit

type

Description

B Dot clock input pin

A Dot clock output pin

B Horizontal sync signal input pin. The active level is programmable.

B Vertical sync signal input pin. The active level is programmable.

Display output control signal input pin. Input a high level signal to

B

enable display output. Input a low level signal to set the display

output (DA3-0, VOBA, DB3-0, VOBB pin output) to inactive level.

The active level is programmable.

Color signal output pins. In straight output mode, the all-dot signal

A is output. In demultiplexed output mode, the even dot signal is out-

put. The active level is programmable.

Display period signal output pin. In straight output mode, the all-

A

dot display period signal is output. In demultiplexed output mode,

the even dot display period signal is output. The active level is pro-

grammable.

Color signal output pins. In demultiplexed output mode, the odd

A dot signal is output. In straight output mode, the output is fixed at

inactive level. The active level is programmable.

Display period signal output pin. In demultiplexed output mode, the

A odd dot display period signal is output. In straight output mode, the

output is fixed at inactive level. The active level is programmable.

A

Busy signal output pin. During internal VRAM fill operation, or in-

ternal command ROM transfer, a high level signal is output.

C

Chip select pin. During serial instruction transfer, a low level signal

is input.

C Serial data input pin.

C Shift clock input pin for serial transfer.

C Reset signal input pin. Input a low level signal at power-on.

C

Test signal input pin. Input a (fixed) high level signal during normal

operation.

 +3.3 V power supply pins.

 Ground pins

B

Test clock input pin. Input a (fixed) low level signal during normal

operation.

4

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