MB90092PF Просмотр технического описания (PDF) - Fujitsu

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MB90092PF

ON-Screen Display Controller

Fujitsu 

MB90092

s PIN DESCRIPTION

Pin no.

Pin name

I/O

Circuit

type

Function

1 TESTI

Test signal input pin. Input High level signal during normal operation.

I

B

This pin also can be used as a reset signal input pin by Low-level input

to the TEST pin. That is effective only after release of power-on reset.

This pin is a hysteresis input with an internal pull-up resistor.

2 VOC

O

C

Character interval signal output pin.

The output signal represents the character dot output interval.

3 VOB

Character/background internal signal output pin.

O

C

During internal synchronization control operation, the output signal rep-

resents the character, character background, line background, or screen

background output interval.

5B

6R

7G

Color signal output pins.

O

C These pins output the character, character background, line back-

ground, and screen background color signals.

8 CS

Chip select pin.

I

B

For serial transfer, set this pin to the Low level.

This pin is also used to release a power-on reset.

The pin is a hysteresis input with an internal pull-up resistor.

9 SCLK

I

B

Shift clock input pin for serial transfer.

This pin is a hysteresis input with an internal pull-up resistor.

10 SIN

I

B

Serial data input pin.

The pin is a hysteresis input with an internal pull-up resistor.

12 EXHSYN I

External horizontal sync signal input pin.

Input negative logic signal.

B This pin can also serve as a composite sync signal input pin depending

on the internal register setting.

The pin is a hysteresis input with an internal pull-up resistor.

13 EXVSYN I

External vertical sync signal input pin.

Input negative logic signal.

B Input to this pin is disabled when composite sync signal input has been

selected by setting the internal register. The pin is a hysteresis input with

an internal pull-up resistor.

14 HSYNC O

Horizontal sync signal output pin.

This pin can also output composite sync signals depending on the inter-

C nal register setting.

The pin outputs the signal (FSC) resulting from dividing the 4FSC clock

frequency by setting the TEST pin to the Low level.

15 VSYNC O

Vertical sync signal output pin.

This pin is fixed at the High level when composite sync signal output has

C been selected by setting the internal register.

The pin outputs the dot clock oscillator signal when the TEST pin goes

into Low.

16 VBLNK

O

C

Vertical blanking interval signal output pin.

This pin outputs the Low-level signal in the vertical blanking interval.

(Continued)

5

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